files.tsarm revision 1.5
1 # $NetBSD: files.tsarm,v 1.5 2005/01/09 21:40:02 joff Exp $ 2 # 3 # First try for arm-specific configuration info 4 # 5 6 # Use the generic ARM soft interrupt code. 7 file arch/arm/arm/softintr.c 8 file arch/evbarm/tsarm/tsarm_machdep.c 9 10 # EP93xx Processor CPU support 11 include "arch/arm/ep93xx/files.ep93xx" 12 13 attach epsoc at mainbus 14 15 attach epcom at epsoc with epcom_ts 16 file arch/evbarm/tsarm/epcom_ts.c 17 18 define tspldbus {} 19 device tspld: isabus, tspldbus, sysmon_wdog 20 attach tspld at mainbus 21 file arch/evbarm/tsarm/tspld.c tspld 22 23 file arch/evbarm/tsarm/isa/isa_machdep.c isa 24 file arch/evbarm/tsarm/isa/isa_io.c isa 25 file arch/evbarm/tsarm/isa/isa_io_asm.S isa 26 27 attach wdc at tspldbus with wdc_ts 28 file arch/evbarm/tsarm/wdc_ts.c wdc_ts 29 30 device tsrtc: mc146818 31 attach tsrtc at tspldbus 32 file arch/evbarm/tsarm/tsrtc.c tsrtc 33 34 device tslcd: hd44780 35 attach tslcd at tspldbus 36 file arch/evbarm/tsarm/tslcd.c tslcd 37 38 # XXXX pcic here because it needs to be late. The catch: pcic needs 39 # to be late, so devices which attach to it are attached late. But it 40 # needs to be before its isa and pci attachments. This answer is 41 # non-optimal, but I don't have a better answer right now. 42 43 # PCIC pcmcia controller 44 # XXX this needs to be done very late, so it's done here. This feels 45 # like a kludge, but it might be for the best. 46 47 defparam PCIC_ISA_ALLOC_IOBASE 48 defparam PCIC_ISA_ALLOC_IOSIZE 49 defparam PCIC_ISA_INTR_ALLOC_MASK 50 51 device pcic: pcmciabus 52 file dev/ic/i82365.c pcic 53 54 # PCIC pcmcia controller on ISA bus. 55 attach pcic at isa with pcic_isa 56 file dev/isa/i82365_isa.c pcic_isa 57 58 # Code common to ISA and ISAPnP attachments 59 file dev/isa/i82365_isasubr.c pcic_isa 60 61 # this wants to be probed as late as possible. 62 # 63 # Machine-independent PCMCIA drivers 64 # 65 include "dev/pcmcia/files.pcmcia" 66
Indexes created Tue Sep 23 14:10:03 GMT 2025