g42xxeb_start.S revision 1.1.2.2
1 1.1.2.2 skrll /* $NetBSD: g42xxeb_start.S,v 1.1.2.2 2005/03/04 16:38:25 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /* 4 1.1.2.2 skrll * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 5 1.1.2.2 skrll * Written by Hiroyuki Bessho for Genetec Corporation. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 3. The name of Genetec Corporation may not be used to endorse or 16 1.1.2.2 skrll * promote products derived from this software without specific prior 17 1.1.2.2 skrll * written permission. 18 1.1.2.2 skrll * 19 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 20 1.1.2.2 skrll * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1.2.2 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1.2.2 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 23 1.1.2.2 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1.2.2 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1.2.2 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1.2.2 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1.2.2 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1.2.2 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1.2.2 skrll * POSSIBILITY OF SUCH DAMAGE. 30 1.1.2.2 skrll */ 31 1.1.2.2 skrll 32 1.1.2.2 skrll #include <machine/asm.h> 33 1.1.2.2 skrll #include <arm/armreg.h> 34 1.1.2.2 skrll #include <arm/arm32/pte.h> 35 1.1.2.2 skrll #include <arm/arm32/pmap.h> /* for PMAP_DOMAIN_KERNEL */ 36 1.1.2.2 skrll 37 1.1.2.2 skrll #ifndef SDRAM_START 38 1.1.2.2 skrll #define SDRAM_START 0xa0000000 39 1.1.2.2 skrll #endif 40 1.1.2.2 skrll 41 1.1.2.2 skrll /* 42 1.1.2.2 skrll * CPWAIT -- Canonical method to wait for CP15 update. 43 1.1.2.2 skrll * NOTE: Clobbers the specified temp reg. 44 1.1.2.2 skrll * copied from arm/arm/cpufunc_asm_xscale.S 45 1.1.2.2 skrll * XXX: better be in a common header file. 46 1.1.2.2 skrll */ 47 1.1.2.2 skrll #define CPWAIT_BRANCH \ 48 1.1.2.2 skrll sub pc, pc, #4 49 1.1.2.2 skrll 50 1.1.2.2 skrll #define CPWAIT(tmp) \ 51 1.1.2.2 skrll mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 52 1.1.2.2 skrll mov tmp, tmp /* wait for it to complete */ ;\ 53 1.1.2.2 skrll CPWAIT_BRANCH /* branch to next insn */ 54 1.1.2.2 skrll 55 1.1.2.2 skrll /* 56 1.1.2.2 skrll * Kernel start routine for G4255EB (TWINTAIL) 57 1.1.2.2 skrll * this code is excuted at the very first after the kernel is loaded 58 1.1.2.2 skrll * by RedBoot. 59 1.1.2.2 skrll */ 60 1.1.2.2 skrll .text 61 1.1.2.2 skrll 62 1.1.2.2 skrll .global _C_LABEL(g42xxeb_start) 63 1.1.2.2 skrll _C_LABEL(g42xxeb_start): 64 1.1.2.2 skrll /* Are we running on ROM ? */ 65 1.1.2.2 skrll cmp pc, #0x06000000 66 1.1.2.2 skrll bhi g42xxeb_start_ram 67 1.1.2.2 skrll 68 1.1.2.2 skrll /* move me to RAM 69 1.1.2.2 skrll * XXX: we can use memcpy if it is PIC 70 1.1.2.2 skrll */ 71 1.1.2.2 skrll ldr r1, Lcopy_size 72 1.1.2.2 skrll adr r0, _C_LABEL(g42xxeb_start) 73 1.1.2.2 skrll add r1, r1, #3 74 1.1.2.2 skrll mov r1, r1, LSR #2 75 1.1.2.2 skrll mov r2, #SDRAM_START 76 1.1.2.2 skrll add r2, r2, #0x00200000 77 1.1.2.2 skrll mov r4, r2 78 1.1.2.2 skrll 79 1.1.2.2 skrll 5: ldr r3,[r0],#4 80 1.1.2.2 skrll str r3,[r2],#4 81 1.1.2.2 skrll subs r1,r1,#1 82 1.1.2.2 skrll bhi 5b 83 1.1.2.2 skrll 84 1.1.2.2 skrll /* Jump to RAM */ 85 1.1.2.2 skrll ldr r0, Lstart_off 86 1.1.2.2 skrll add pc, r4, r0 87 1.1.2.2 skrll 88 1.1.2.2 skrll Lcopy_size: .word _edata-_C_LABEL(g42xxeb_start) 89 1.1.2.2 skrll Lstart_off: .word g42xxeb_start_ram-_C_LABEL(g42xxeb_start) 90 1.1.2.2 skrll 91 1.1.2.2 skrll g42xxeb_start_ram: 92 1.1.2.2 skrll /* 93 1.1.2.2 skrll * Kernel is loaded in SDRAM (0xa0200000..), and is expected to run 94 1.1.2.2 skrll * in VA 0xc0200000.. 95 1.1.2.2 skrll */ 96 1.1.2.2 skrll 97 1.1.2.2 skrll mrc p15, 0, r0, c2, c0, 0 /* get ttb prepared by redboot */ 98 1.1.2.2 skrll adr r4, mmu_init_table2 99 1.1.2.2 skrll 100 1.1.2.2 skrll #ifdef BUILD_STARTUP_PAGETABLE 101 1.1.2.2 skrll mrc p15, 0, r2, c1, c0, 0 102 1.1.2.2 skrll tst r2, #CPU_CONTROL_MMU_ENABLE /* we already have a page table? */ 103 1.1.2.2 skrll bne 3f 104 1.1.2.2 skrll 105 1.1.2.2 skrll /* build page table from scratch */ 106 1.1.2.2 skrll ldr r0, Lstartup_pagetable 107 1.1.2.2 skrll adr r4, mmu_init_table 108 1.1.2.2 skrll #endif 109 1.1.2.2 skrll b 3f 110 1.1.2.2 skrll 111 1.1.2.2 skrll 2: 112 1.1.2.2 skrll str r3, [r0, r2] 113 1.1.2.2 skrll add r2, r2, #4 114 1.1.2.2 skrll add r3, r3, #(L1_S_SIZE) 115 1.1.2.2 skrll adds r1, r1, #-1 116 1.1.2.2 skrll bhi 2b 117 1.1.2.2 skrll 3: 118 1.1.2.2 skrll ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */ 119 1.1.2.2 skrll cmp r1, #0 120 1.1.2.2 skrll bne 2b 121 1.1.2.2 skrll 122 1.1.2.2 skrll mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 123 1.1.2.2 skrll mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 124 1.1.2.2 skrll 125 1.1.2.2 skrll /* Set the Domain Access register. Very important! */ 126 1.1.2.2 skrll mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 127 1.1.2.2 skrll mcr p15, 0, r0, c3, c0, 0 128 1.1.2.2 skrll 129 1.1.2.2 skrll /* Enable MMU */ 130 1.1.2.2 skrll mrc p15, 0, r0, c1, c0, 0 131 1.1.2.2 skrll orr r0, r0, #CPU_CONTROL_MMU_ENABLE 132 1.1.2.2 skrll mcr p15, 0, r0, c1, c0, 0 133 1.1.2.2 skrll CPWAIT(r0) 134 1.1.2.2 skrll 135 1.1.2.2 skrll /* Jump to kernel code in TRUE VA */ 136 1.1.2.2 skrll adr r0, Lstart 137 1.1.2.2 skrll ldr pc, [r0] 138 1.1.2.2 skrll 139 1.1.2.2 skrll Lstart: 140 1.1.2.2 skrll .word start 141 1.1.2.2 skrll 142 1.1.2.2 skrll #define MMU_INIT(va,pa,n_sec,attr) \ 143 1.1.2.2 skrll .word n_sec ; \ 144 1.1.2.2 skrll .word 4*((va)>>L1_S_SHIFT) ; \ 145 1.1.2.2 skrll .word (pa)|(attr) ; 146 1.1.2.2 skrll 147 1.1.2.2 skrll #ifdef BUILD_STARTUP_PAGETABLE 148 1.1.2.2 skrll #ifndef STARTUP_PAGETABLE_ADDR 149 1.1.2.2 skrll #define STARTUP_PAGETABLE_ADDR 0xa0004000 150 1.1.2.2 skrll #endif 151 1.1.2.2 skrll Lstartup_pagetable .word STARTUP_PAGETABLE_ADDR 152 1.1.2.2 skrll mmu_init_table: 153 1.1.2.2 skrll /* fill all table VA==PA */ 154 1.1.2.2 skrll MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW)) 155 1.1.2.2 skrll /* map SDRAM VA==PA, WT cacheable */ 156 1.1.2.2 skrll MMU_INIT(SDRAM_START, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 157 1.1.2.2 skrll #endif 158 1.1.2.2 skrll mmu_init_table2: 159 1.1.2.2 skrll /* map VA 0xc0000000..0xc3ffffff to PA 0xa0000000..0xa3ffffff */ 160 1.1.2.2 skrll MMU_INIT(0xc0000000, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW)) 161 1.1.2.2 skrll 162 1.1.2.2 skrll .word 0 /* end of table */ 163
Indexes created Tue Oct 28 07:09:57 GMT 2025