i80321_mainbus.c revision 1.1
1 /* $NetBSD: i80321_mainbus.c,v 1.1 2006/04/16 02:22:33 nonaka Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: i80321_mainbus.c,v 1.1 2006/04/16 02:22:33 nonaka Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <machine/autoconf.h> 46 #include <machine/bus.h> 47 48 #include <evbarm/hdl_g/hdlgreg.h> 49 #include <evbarm/hdl_g/hdlgvar.h> 50 51 #include <arm/xscale/i80321reg.h> 52 #include <arm/xscale/i80321var.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 int hdlg_mainbus_match(struct device *, struct cfdata *, void *); 58 void hdlg_mainbus_attach(struct device *, struct device *, void *); 59 60 CFATTACH_DECL(iopxs_mainbus, sizeof(struct i80321_softc), 61 hdlg_mainbus_match, hdlg_mainbus_attach, NULL, NULL); 62 63 /* There can be only one. */ 64 int hdlg_mainbus_found; 65 66 int 67 hdlg_mainbus_match(struct device *parent, struct cfdata *cf, void *aux) 68 { 69 70 if (hdlg_mainbus_found) 71 return 0; 72 return 1; 73 } 74 75 void 76 hdlg_mainbus_attach(struct device *parent, struct device *self, void *aux) 77 { 78 struct i80321_softc *sc = (void *) self; 79 pcireg_t b0u, b0l, b1u, b1l; 80 paddr_t memstart; 81 psize_t memsize; 82 83 hdlg_mainbus_found = 1; 84 85 /* 86 * Fill in the space tag for the i80321's own devices, 87 * and hand-craft the space handle for it (the device 88 * was mapped during early bootstrap). 89 */ 90 i80321_bs_init(&i80321_bs_tag, sc); 91 sc->sc_st = &i80321_bs_tag; 92 sc->sc_sh = HDLG_80321_VBASE; 93 94 /* 95 * Slice off a subregion for the Memory Controller -- we need it 96 * here in order read the memory size. 97 */ 98 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE, 99 VERDE_MCU_SIZE, &sc->sc_mcu_sh)) 100 panic("%s: unable to subregion MCU registers", 101 device_xname(&sc->sc_dev)); 102 103 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE, 104 VERDE_ATU_SIZE, &sc->sc_atu_sh)) 105 panic("%s: unable to subregion ATU registers", 106 device_xname(&sc->sc_dev)); 107 108 /* 109 * We have mapped the PCI I/O windows in the early bootstrap phase. 110 */ 111 sc->sc_iow_vaddr = HDLG_IOW_VBASE; 112 113 /* 114 * Check the configuration of the ATU to see if another BIOS 115 * has configured us. If a PC BIOS didn't configure us, then: 116 * IQ80321: BAR0 00000000.0000000c BAR1 is 00000000.8000000c. 117 * IQ31244: BAR0 00000000.00000004 BAR1 is 00000000.0000000c. 118 * If a BIOS has configured us, at least one of those should be 119 * different. This is pretty fragile, but it's not clear what 120 * would work better. 121 */ 122 b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x0); 123 b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x4); 124 b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x8); 125 b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0xc); 126 b0l &= PCI_MAPREG_MEM_ADDR_MASK; 127 b0u &= PCI_MAPREG_MEM_ADDR_MASK; 128 b1l &= PCI_MAPREG_MEM_ADDR_MASK; 129 b1u &= PCI_MAPREG_MEM_ADDR_MASK; 130 131 if ((b0u != b1u) || (b0l != 0) || ((b1l & ~0x80000000U) != 0)) 132 sc->sc_is_host = 0; 133 else 134 sc->sc_is_host = 1; 135 136 aprint_naive(": i80219 I/O Processor\n"); 137 aprint_normal(": i80219 I/O Processor, acting as PCI %s\n", 138 sc->sc_is_host ? "host" : "slave"); 139 140 i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize); 141 142 /* 143 * We set up the Inbound Windows as follows: 144 * 145 * 0 Access to i80219 PMMRs 146 * 147 * 1 Reserve space for private devices 148 * 149 * 2 RAM access 150 * 151 * 3 Unused. 152 * 153 * This chunk needs to be customized for each IOP321 application. 154 */ 155 #if 0 156 sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE; 157 sc->sc_iwin[0].iwin_base_hi = 0; 158 sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE; 159 sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE; 160 #endif 161 162 if (sc->sc_is_host) { 163 /* Map PCI:Local 1:1. */ 164 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE | 165 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 166 PCI_MAPREG_MEM_TYPE_64BIT; 167 sc->sc_iwin[1].iwin_base_hi = 0; 168 } else { 169 sc->sc_iwin[1].iwin_base_lo = 0; 170 sc->sc_iwin[1].iwin_base_hi = 0; 171 } 172 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE; 173 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE; 174 175 if (sc->sc_is_host) { 176 sc->sc_iwin[2].iwin_base_lo = memstart | 177 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 178 PCI_MAPREG_MEM_TYPE_64BIT; 179 sc->sc_iwin[2].iwin_base_hi = 0; 180 } else { 181 sc->sc_iwin[2].iwin_base_lo = 0; 182 sc->sc_iwin[2].iwin_base_hi = 0; 183 } 184 sc->sc_iwin[2].iwin_xlate = memstart; 185 sc->sc_iwin[2].iwin_size = memsize; 186 187 if (sc->sc_is_host) { 188 sc->sc_iwin[3].iwin_base_lo = 0 | 189 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 190 PCI_MAPREG_MEM_TYPE_64BIT; 191 } else { 192 sc->sc_iwin[3].iwin_base_lo = 0; 193 } 194 sc->sc_iwin[3].iwin_base_hi = 0; 195 sc->sc_iwin[3].iwin_xlate = 0; 196 sc->sc_iwin[3].iwin_size = 0; 197 198 /* 199 * We set up the Outbound Windows as follows: 200 * 201 * 0 Access to private PCI space. 202 * 203 * 1 Unused. 204 */ 205 sc->sc_owin[0].owin_xlate_lo = 206 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo); 207 sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi; 208 209 /* 210 * Set the Secondary Outbound I/O window to map 211 * to PCI address 0 for all 64K of the I/O space. 212 */ 213 sc->sc_ioout_xlate = 0; 214 sc->sc_ioout_xlate_offset = 0x1000; 215 216 /* 217 * Initialize the interrupt part of our PCI chipset tag. 218 */ 219 hdlg_pci_init(&sc->sc_pci_chipset, sc); 220 221 i80321_attach(sc); 222 } 223
Indexes created Fri Sep 26 08:10:20 GMT 2025