1 /* $NetBSD: i80321_mainbus.c,v 1.3 2012/02/12 16:31:01 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: i80321_mainbus.c,v 1.3 2012/02/12 16:31:01 matt Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <machine/autoconf.h> 46 #include <sys/bus.h> 47 48 #include <evbarm/hdl_g/hdlgreg.h> 49 #include <evbarm/hdl_g/hdlgvar.h> 50 51 #include <arm/xscale/i80321reg.h> 52 #include <arm/xscale/i80321var.h> 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcidevs.h> 56 57 int hdlg_mainbus_match(device_t, cfdata_t, void *); 58 void hdlg_mainbus_attach(device_t, device_t, void *); 59 60 CFATTACH_DECL_NEW(iopxs_mainbus, sizeof(struct i80321_softc), 61 hdlg_mainbus_match, hdlg_mainbus_attach, NULL, NULL); 62 63 /* There can be only one. */ 64 int hdlg_mainbus_found; 65 66 int 67 hdlg_mainbus_match(device_t parent, cfdata_t cf, void *aux) 68 { 69 70 if (hdlg_mainbus_found) 71 return 0; 72 return 1; 73 } 74 75 void 76 hdlg_mainbus_attach(device_t parent, device_t self, void *aux) 77 { 78 struct i80321_softc *sc = device_private(self); 79 pcireg_t b0u, b0l, b1u, b1l; 80 paddr_t memstart; 81 psize_t memsize; 82 83 hdlg_mainbus_found = 1; 84 sc->sc_dev = self; 85 86 /* 87 * Fill in the space tag for the i80321's own devices, 88 * and hand-craft the space handle for it (the device 89 * was mapped during early bootstrap). 90 */ 91 i80321_bs_init(&i80321_bs_tag, sc); 92 sc->sc_st = &i80321_bs_tag; 93 sc->sc_sh = HDLG_80321_VBASE; 94 95 /* 96 * Slice off a subregion for the Memory Controller -- we need it 97 * here in order read the memory size. 98 */ 99 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_MCU_BASE, 100 VERDE_MCU_SIZE, &sc->sc_mcu_sh)) 101 panic("%s: unable to subregion MCU registers", 102 device_xname(sc->sc_dev)); 103 104 if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE, 105 VERDE_ATU_SIZE, &sc->sc_atu_sh)) 106 panic("%s: unable to subregion ATU registers", 107 device_xname(sc->sc_dev)); 108 109 /* 110 * We have mapped the PCI I/O windows in the early bootstrap phase. 111 */ 112 sc->sc_iow_vaddr = HDLG_IOW_VBASE; 113 114 /* 115 * Check the configuration of the ATU to see if another BIOS 116 * has configured us. If a PC BIOS didn't configure us, then: 117 * IQ80321: BAR0 00000000.0000000c BAR1 is 00000000.8000000c. 118 * IQ31244: BAR0 00000000.00000004 BAR1 is 00000000.0000000c. 119 * If a BIOS has configured us, at least one of those should be 120 * different. This is pretty fragile, but it's not clear what 121 * would work better. 122 */ 123 b0l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x0); 124 b0u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x4); 125 b1l = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0x8); 126 b1u = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, PCI_MAPREG_START+0xc); 127 b0l &= PCI_MAPREG_MEM_ADDR_MASK; 128 b0u &= PCI_MAPREG_MEM_ADDR_MASK; 129 b1l &= PCI_MAPREG_MEM_ADDR_MASK; 130 b1u &= PCI_MAPREG_MEM_ADDR_MASK; 131 132 if ((b0u != b1u) || (b0l != 0) || ((b1l & ~0x80000000U) != 0)) 133 sc->sc_is_host = 0; 134 else 135 sc->sc_is_host = 1; 136 137 aprint_naive(": i80219 I/O Processor\n"); 138 aprint_normal(": i80219 I/O Processor, acting as PCI %s\n", 139 sc->sc_is_host ? "host" : "slave"); 140 141 i80321_intr_evcnt_attach(); 142 143 i80321_sdram_bounds(sc->sc_st, sc->sc_mcu_sh, &memstart, &memsize); 144 145 /* 146 * We set up the Inbound Windows as follows: 147 * 148 * 0 Access to i80219 PMMRs 149 * 150 * 1 Reserve space for private devices 151 * 152 * 2 RAM access 153 * 154 * 3 Unused. 155 * 156 * This chunk needs to be customized for each IOP321 application. 157 */ 158 #if 0 159 sc->sc_iwin[0].iwin_base_lo = VERDE_PMMR_BASE; 160 sc->sc_iwin[0].iwin_base_hi = 0; 161 sc->sc_iwin[0].iwin_xlate = VERDE_PMMR_BASE; 162 sc->sc_iwin[0].iwin_size = VERDE_PMMR_SIZE; 163 #endif 164 165 if (sc->sc_is_host) { 166 /* Map PCI:Local 1:1. */ 167 sc->sc_iwin[1].iwin_base_lo = VERDE_OUT_XLATE_MEM_WIN0_BASE | 168 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 169 PCI_MAPREG_MEM_TYPE_64BIT; 170 sc->sc_iwin[1].iwin_base_hi = 0; 171 } else { 172 sc->sc_iwin[1].iwin_base_lo = 0; 173 sc->sc_iwin[1].iwin_base_hi = 0; 174 } 175 sc->sc_iwin[1].iwin_xlate = VERDE_OUT_XLATE_MEM_WIN0_BASE; 176 sc->sc_iwin[1].iwin_size = VERDE_OUT_XLATE_MEM_WIN_SIZE; 177 178 if (sc->sc_is_host) { 179 sc->sc_iwin[2].iwin_base_lo = memstart | 180 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 181 PCI_MAPREG_MEM_TYPE_64BIT; 182 sc->sc_iwin[2].iwin_base_hi = 0; 183 } else { 184 sc->sc_iwin[2].iwin_base_lo = 0; 185 sc->sc_iwin[2].iwin_base_hi = 0; 186 } 187 sc->sc_iwin[2].iwin_xlate = memstart; 188 sc->sc_iwin[2].iwin_size = memsize; 189 190 if (sc->sc_is_host) { 191 sc->sc_iwin[3].iwin_base_lo = 0 | 192 PCI_MAPREG_MEM_PREFETCHABLE_MASK | 193 PCI_MAPREG_MEM_TYPE_64BIT; 194 } else { 195 sc->sc_iwin[3].iwin_base_lo = 0; 196 } 197 sc->sc_iwin[3].iwin_base_hi = 0; 198 sc->sc_iwin[3].iwin_xlate = 0; 199 sc->sc_iwin[3].iwin_size = 0; 200 201 /* 202 * We set up the Outbound Windows as follows: 203 * 204 * 0 Access to private PCI space. 205 * 206 * 1 Unused. 207 */ 208 sc->sc_owin[0].owin_xlate_lo = 209 PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo); 210 sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi; 211 212 /* 213 * Set the Secondary Outbound I/O window to map 214 * to PCI address 0 for all 64K of the I/O space. 215 */ 216 sc->sc_ioout_xlate = 0; 217 sc->sc_ioout_xlate_offset = 0x1000; 218 219 /* 220 * Initialize the interrupt part of our PCI chipset tag. 221 */ 222 hdlg_pci_init(&sc->sc_pci_chipset, sc); 223 224 i80321_attach(sc); 225 } 226
Indexes created Sat Sep 20 22:09:52 GMT 2025