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      1 /*	$NetBSD: ixdp425_start.S,v 1.7 2011/01/31 06:28:04 matt Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2003
      5  *	Ichiro FUKUHARA <ichiro (at) ichiro.org>.
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
     21  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     27  * SUCH DAMAGE.
     28  */
     29 #include <machine/asm.h>
     30 #include <arm/armreg.h>
     31 #include "assym.h"
     32 
     33 #include <arm/xscale/ixp425reg.h>
     34 
     35 RCSID("$NetBSD: ixdp425_start.S,v 1.7 2011/01/31 06:28:04 matt Exp $")
     36 
     37 	.section .start,"ax",%progbits
     38 
     39 	.global	_C_LABEL(ixdp425_start)
     40 _C_LABEL(ixdp425_start):
     41         /*
     42          * We will go ahead and disable the MMU here so that we don't
     43          * have to worry about flushing caches, etc.
     44          *
     45          * Note that we may not currently be running VA==PA, which means
     46          * we'll need to leap to the next insn after disabing the MMU.
     47          */
     48         adr     r8, Lunmapped
     49         bic     r8, r8, #0xff000000     /* clear upper 8 bits */
     50         orr     r8, r8, #0x10000000     /* OR in physical base address */
     51 
     52 	/*
     53 	 * Setup coprocessor 15.
     54 	 */
     55 	/*
     56 	 *IXDP425 with CSR(microengine code produced by Intel Corp.)
     57 	 *  running well on BigEndian, because CSR written on bigendian
     58 	 */
     59         mrc     p15, 0, r2, c1, c0, 0
     60         bic     r2, r2, #CPU_CONTROL_MMU_ENABLE
     61 	orr	r2, r2, #CPU_CONTROL_BEND_ENABLE
     62         mcr     p15, 0, r2, c1, c0, 0
     63 
     64         nop
     65         nop
     66         nop
     67 
     68         mov     pc, r8                  /* Heave-ho! */
     69 
     70 Lunmapped:
     71 	/*
     72 	 * We want to construct a memory map that maps us
     73 	 * VA==PA (SDRAM at 0x10000000). We create these
     74 	 * mappings uncached and unbuffered to be safe.
     75 	 */
     76 
     77 	/*
     78 	 * Step 1: Map the entire address space VA==PA.
     79 	 */
     80 	adr	r0, Ltable
     81 	ldr	r0, [r0]			/* r0 = &l1table */
     82 
     83 	mov	r1, #(L1_TABLE_SIZE / 4)	/* 4096 entry */
     84 	mov	r2, #(L1_S_SIZE)		/* 1MB / section */
     85 	mov	r3, #(L1_S_AP_KRW)		/* kernel read/write */
     86 	orr	r3, r3, #(L1_TYPE_S)		/* L1 entry is section */
     87 1:
     88 	str	r3, [r0], #0x04
     89 	add	r3, r3, r2
     90 	subs	r1, r1, #1
     91 	bgt	1b
     92 
     93         /*
     94          * Step 2: Map VA 0xc0000000->0xc3ffffff to PA 0x10000000->0x13ffffff.
     95          */
     96         adr     r0, Ltable                      /* r0 = &l1table */
     97         ldr     r0, [r0]
     98 
     99         mov     r3, #(L1_S_AP_KRW)
    100         orr     r3, r3, #(L1_TYPE_S)
    101         orr     r3, r3, #0x10000000
    102         add     r0, r0, #(0xc00 * 4)            /* offset to 0xc00xxxxx */
    103         mov     r1, #0x40                       /* 64MB */
    104 1:
    105         str     r3, [r0], #0x04
    106         add     r3, r3, r2
    107         subs    r1, r1, #1
    108         bgt     1b
    109 
    110 	/*
    111 	 * Step 3: Map VA 0xf0000000->0xf0100000 to PA 0xc8000000->0xc8100000.
    112 	 */
    113 	adr	r0, Ltable			/* r0 = &l1table */
    114 	ldr	r0, [r0]
    115 
    116 	add	r0, r0, #(0xf00 * 4)		/* offset to 0xf0000000 */
    117 	mov	r3, #0xc8000000
    118 	add	r3, r3, #0x00100000
    119 	orr	r3, r3, #(L1_S_AP_KRW)
    120 	orr	r3, r3, #(L1_TYPE_S)
    121 	str	r3, [r0]
    122 
    123 	/*
    124 	 * Step 4: Map VA 0xf0200000->0xf0300000 to PA 0xcc000000->0xcc100000.
    125 	 */
    126 	adr	r0, Ltable			/* r0 = &l1table */
    127 	ldr	r0, [r0]
    128 
    129 	add	r0, r0, #(0xf00 * 4)		/* offset to 0xf0200000 */
    130 	add	r0, r0, #(0x002 * 4)
    131 	mov	r3, #0xcc000000
    132 	add	r3, r3, #0x00100000
    133 	orr	r3, r3, #(L1_S_AP_KRW)
    134 	orr	r3, r3, #(L1_TYPE_S)
    135 	str	r3, [r0]
    136 
    137 	/* OK!  Page table is set up.  Give it to the CPU. */
    138 	adr	r0, Ltable
    139 	ldr	r0, [r0]
    140 	mcr	p15, 0, r0, c2, c0, 0
    141 
    142 	/* Flush the old TLBs, just in case. */
    143 	mcr	p15, 0, r0, c8, c7, 0
    144 
    145 	/* Set the Domain Access register.  Very important! */
    146 	mov	r0, #1
    147 	mcr	p15, 0, r0, c3, c0, 0
    148 
    149 	/* Get ready to jump to the "real" kernel entry point... */
    150 	ldr	r1, Lstart
    151 	mov	r1, r1			/* Make sure the load completes! */
    152 
    153 	/* OK, let's enable the MMU. */
    154 	mrc	p15, 0, r2, c1, c0, 0
    155 	orr	r2, r2, #CPU_CONTROL_MMU_ENABLE
    156 	orr	r2, r2, #CPU_CONTROL_BEND_ENABLE
    157 	mcr	p15, 0, r2, c1, c0, 0
    158 
    159 	nop
    160 	nop
    161 	nop
    162 
    163 	/* CPWAIT sequence to make sure the MMU is on... */
    164 	mrc	p15, 0, r2, c2, c0, 0	/* arbitrary read of CP15 */
    165 	mov	r2, r2			/* force it to complete */
    166 	mov	pc, r1			/* leap to kernel entry point! */
    167 
    168 Ltable:
    169 	.word	0x10200000 - 0x4000
    170 
    171 Lstart:
    172 	.word	start
    173