1 /* $NetBSD: nappi_nppb.c,v 1.14 2020/06/17 06:59:45 thorpej Exp $ */ 2 /* 3 * Copyright (c) 2002, 2003 4 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: nappi_nppb.c,v 1.14 2020/06/17 06:59:45 thorpej Exp $"); 31 32 #include "pci.h" 33 #include "opt_pci.h" 34 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 40 #include <sys/bus.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciconf.h> 46 47 static int nppbmatch(device_t, cfdata_t, void *); 48 static void nppbattach(device_t, device_t, void *); 49 50 int nppb_intr(void *); /* XXX into i21555var.h */ 51 52 CFATTACH_DECL_NEW(nppb, 0, 53 nppbmatch, nppbattach, NULL, NULL); 54 55 #define NPPB_MMBA 0x10 56 #define NPPB_IOBA 0x14 57 58 #define CSR_READ_1(sc, reg) \ 59 bus_space_read_1(sc->sc_st, sc->sc_sh, reg) 60 #define CSR_READ_2(sc, reg) \ 61 bus_space_read_2(sc->sc_st, sc->sc_sh, reg) 62 #define CSR_READ_4(sc, reg) \ 63 bus_space_read_4(sc->sc_st, sc->sc_sh, reg) 64 65 #define CSR_WRITE_1(sc, reg, val) \ 66 bus_space_write_1(sc->sc_st, sc->sc_sh, reg, val) 67 #define CSR_WRITE_2(sc, reg, val) \ 68 bus_space_write_2(sc->sc_st, sc->sc_sh, reg, val) 69 #define CSR_WRITE_4(sc, reg, val) \ 70 bus_space_write_4(sc->sc_st, sc->sc_sh, reg, val) 71 72 struct nppb_softc { /* XXX into i21555var.h */ 73 bus_space_tag_t sc_st; /* bus space tag */ 74 bus_space_handle_t sc_sh; /* bus space handle */ 75 76 void *sc_ih; /* interrupt handler cookie */ 77 }; 78 79 struct nppb_pci_softc { 80 struct nppb_softc psc_nppb; 81 82 pci_chipset_tag_t psc_pc; /* pci chipset tag */ 83 pcitag_t psc_tag; /* pci register tag */ 84 }; 85 86 static int 87 nppbmatch(device_t parent, cfdata_t cf, void *aux) 88 { 89 struct pci_attach_args *pa = aux; 90 uint32_t class, id; 91 92 class = pa->pa_class; 93 id = pa->pa_id; 94 95 if (PCI_CLASS(class) == PCI_CLASS_BRIDGE && 96 PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_MISC) { 97 switch (PCI_VENDOR(id)) { 98 case PCI_VENDOR_INTEL: 99 switch (PCI_PRODUCT(id)) { 100 case PCI_PRODUCT_INTEL_21555: 101 return(1); 102 } 103 break; 104 } 105 } 106 return(0); 107 } 108 109 static void 110 nppbattach(device_t parent, device_t self, void *aux) 111 { 112 struct nppb_pci_softc *psc = device_private(self); 113 struct nppb_softc *sc = &psc->psc_nppb; 114 struct pci_attach_args *pa = aux; 115 pci_chipset_tag_t pc = pa->pa_pc; 116 pci_intr_handle_t ih; 117 const char *intrstr = NULL; 118 char devinfo[256]; 119 char intrbuf[PCI_INTRSTR_LEN]; 120 121 bus_space_tag_t iot, memt; 122 bus_space_handle_t ioh, memh; 123 int ioh_valid, memh_valid; 124 125 psc->psc_pc = pc; 126 psc->psc_tag = pa->pa_tag; 127 128 snprintf(devinfo, sizeof(devinfo), "21555 Non-Transparent PCI-PCI Bridge"); 129 aprint_normal(": %s, rev %d\n", devinfo, PCI_REVISION(pa->pa_class)); 130 131 /* Make sure bus-mastering is enabled. */ 132 pci_conf_write(psc->psc_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 133 pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 134 PCI_COMMAND_MASTER_ENABLE); 135 136 /* Chip Reset */ 137 pci_conf_write(psc->psc_pc, pa->pa_tag, 0xD8, 0x03); 138 139 /* Map control/status registers */ 140 ioh_valid = (pci_mapreg_map(pa, NPPB_IOBA, 141 PCI_MAPREG_TYPE_IO, 0, 142 &iot, &ioh, NULL, NULL) == 0); 143 memh_valid = (pci_mapreg_map(pa, NPPB_MMBA, 144 PCI_MAPREG_TYPE_MEM | 145 PCI_MAPREG_MEM_TYPE_32BIT, 146 0, &memt, &memh, NULL, NULL) == 0); 147 148 if (memh_valid) { 149 sc->sc_st = memt; 150 sc->sc_sh = memh; 151 } else if (ioh_valid) { 152 sc->sc_st = iot; 153 sc->sc_sh = ioh; 154 } else { 155 printf(": unable to map device registers\n"); 156 return; 157 } 158 159 /* Map and establish our interrupt */ 160 if (pci_intr_map(pa, &ih)) { 161 printf("%s: couldn't map interrupt\n", device_xname(self)); 162 return; 163 } 164 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 165 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, nppb_intr, sc); 166 if (sc->sc_ih == NULL) { 167 printf("%s: couldn't establish interrupt", 168 device_xname(self)); 169 if (intrstr != NULL) 170 printf(" at %s", intrstr); 171 printf("\n"); 172 return; 173 } 174 printf("%s: interrupting at %s\n", device_xname(self), intrstr); 175 176 } 177 178 /* XXX */ 179 int 180 nppb_intr(void *arg) 181 { 182 #if 0 183 struct nppb_softc *sc = arg; 184 #endif 185 #ifdef PCI_DEBUG 186 printf("nppb_intr assert\n"); 187 #endif 188 return(0); 189 } 190
Indexes created Sat Sep 20 22:09:52 GMT 2025