marvell_start.S revision 1.1.2.2
1 1.1.2.2 yamt /* $NetBSD: marvell_start.S,v 1.1.2.2 2010/10/09 03:31:45 yamt Exp $ */ 2 1.1.2.2 yamt /* 3 1.1.2.2 yamt * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation. 4 1.1.2.2 yamt * All rights reserved. 5 1.1.2.2 yamt * 6 1.1.2.2 yamt * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 1.1.2.2 yamt * Corporation. 8 1.1.2.2 yamt * 9 1.1.2.2 yamt * Redistribution and use in source and binary forms, with or without 10 1.1.2.2 yamt * modification, are permitted provided that the following conditions 11 1.1.2.2 yamt * are met: 12 1.1.2.2 yamt * 1. Redistributions of source code must retain the above copyright 13 1.1.2.2 yamt * notice, this list of conditions and the following disclaimer. 14 1.1.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 15 1.1.2.2 yamt * notice, this list of conditions and the following disclaimer in the 16 1.1.2.2 yamt * documentation and/or other materials provided with the distribution. 17 1.1.2.2 yamt * 3. Neither the name of the project nor the name of SOUM Corporation 18 1.1.2.2 yamt * may be used to endorse or promote products derived from this software 19 1.1.2.2 yamt * without specific prior written permission. 20 1.1.2.2 yamt * 21 1.1.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 1.1.2.2 yamt * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 1.1.2.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 1.1.2.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 1.1.2.2 yamt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 1.1.2.2 yamt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 1.1.2.2 yamt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 1.1.2.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 1.1.2.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 1.1.2.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 1.1.2.2 yamt * POSSIBILITY OF SUCH DAMAGE. 32 1.1.2.2 yamt */ 33 1.1.2.2 yamt /* 34 1.1.2.2 yamt * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 35 1.1.2.2 yamt * Written by Hiroyuki Bessho for Genetec Corporation. 36 1.1.2.2 yamt * 37 1.1.2.2 yamt * Redistribution and use in source and binary forms, with or without 38 1.1.2.2 yamt * modification, are permitted provided that the following conditions 39 1.1.2.2 yamt * are met: 40 1.1.2.2 yamt * 1. Redistributions of source code must retain the above copyright 41 1.1.2.2 yamt * notice, this list of conditions and the following disclaimer. 42 1.1.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 43 1.1.2.2 yamt * notice, this list of conditions and the following disclaimer in the 44 1.1.2.2 yamt * documentation and/or other materials provided with the distribution. 45 1.1.2.2 yamt * 3. The name of Genetec Corporation may not be used to endorse or 46 1.1.2.2 yamt * promote products derived from this software without specific prior 47 1.1.2.2 yamt * written permission. 48 1.1.2.2 yamt * 49 1.1.2.2 yamt * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 50 1.1.2.2 yamt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 1.1.2.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 1.1.2.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 53 1.1.2.2 yamt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 1.1.2.2 yamt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 1.1.2.2 yamt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 1.1.2.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 1.1.2.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 1.1.2.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 1.1.2.2 yamt * POSSIBILITY OF SUCH DAMAGE. 60 1.1.2.2 yamt */ 61 1.1.2.2 yamt 62 1.1.2.2 yamt #include "opt_cputypes.h" 63 1.1.2.2 yamt #include <machine/asm.h> 64 1.1.2.2 yamt #include <arm/armreg.h> 65 1.1.2.2 yamt #include <arm/arm32/pte.h> 66 1.1.2.2 yamt #include <arm/arm32/pmap.h> /* for PMAP_DOMAIN_KERNEL */ 67 1.1.2.2 yamt 68 1.1.2.2 yamt #ifndef SDRAM_START 69 1.1.2.2 yamt #define SDRAM_START 0x00000000 70 1.1.2.2 yamt #endif 71 1.1.2.2 yamt 72 1.1.2.2 yamt /* 73 1.1.2.2 yamt * CPWAIT -- Canonical method to wait for CP15 update. 74 1.1.2.2 yamt * NOTE: Clobbers the specified temp reg. 75 1.1.2.2 yamt * copied from arm/arm/cpufunc_asm_xscale.S 76 1.1.2.2 yamt * XXX: better be in a common header file. 77 1.1.2.2 yamt */ 78 1.1.2.2 yamt #define CPWAIT_BRANCH \ 79 1.1.2.2 yamt sub pc, pc, #4 80 1.1.2.2 yamt 81 1.1.2.2 yamt #define CPWAIT(tmp) \ 82 1.1.2.2 yamt mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 83 1.1.2.2 yamt mov tmp, tmp /* wait for it to complete */ ;\ 84 1.1.2.2 yamt CPWAIT_BRANCH /* branch to next insn */ 85 1.1.2.2 yamt 86 1.1.2.2 yamt /* 87 1.1.2.2 yamt * Kernel start routine for Marvell boards 88 1.1.2.2 yamt * this code is excuted at the very first after the kernel is loaded 89 1.1.2.2 yamt * by U-Boot. 90 1.1.2.2 yamt */ 91 1.1.2.2 yamt .text 92 1.1.2.2 yamt 93 1.1.2.2 yamt .global _C_LABEL(marvell_start) 94 1.1.2.2 yamt _C_LABEL(marvell_start): 95 1.1.2.2 yamt /* The Loader for Marvell board is u-boot. it's running on RAM */ 96 1.1.2.2 yamt /* 97 1.1.2.2 yamt * Kernel is loaded in SDRAM (0x00200000..), and is expected to run 98 1.1.2.2 yamt * in VA 0xc0200000.. 99 1.1.2.2 yamt */ 100 1.1.2.2 yamt 101 1.1.2.2 yamt #ifdef CPU_SHEEVA 102 1.1.2.2 yamt mrc p15, 0, r4, c0, c0, 0 103 1.1.2.2 yamt and r4, r4, #CPU_ID_CPU_MASK 104 1.1.2.2 yamt adr r5, sheeva_cores_start 105 1.1.2.2 yamt adr r6, sheeva_cores_end 106 1.1.2.2 yamt 1: 107 1.1.2.2 yamt cmp r5, r6 108 1.1.2.2 yamt beq 2f 109 1.1.2.2 yamt ldmia r5!, {r7} 110 1.1.2.2 yamt cmp r4, r7 111 1.1.2.2 yamt bne 1b 112 1.1.2.2 yamt 113 1.1.2.2 yamt /* Make sure L2 is disabled */ 114 1.1.2.2 yamt mrc p15, 1, r0, c15, c1, 0 @ Get Marvell Extra Features Register 115 1.1.2.2 yamt bic r0, r0, #0x00400000 @ disable L2 cache 116 1.1.2.2 yamt mcr p15, 1, r0, c15, c1, 0 117 1.1.2.2 yamt 2: 118 1.1.2.2 yamt #endif 119 1.1.2.2 yamt /* save u-boot's args */ 120 1.1.2.2 yamt adr r4, u_boot_args 121 1.1.2.2 yamt nop 122 1.1.2.2 yamt nop 123 1.1.2.2 yamt nop 124 1.1.2.2 yamt stmia r4!, {r0, r1, r2, r3} 125 1.1.2.2 yamt nop 126 1.1.2.2 yamt nop 127 1.1.2.2 yamt nop 128 1.1.2.2 yamt 129 1.1.2.2 yamt /* build page table from scratch */ 130 1.1.2.2 yamt ldr r0, Lstartup_pagetable /* pagetable */ 131 1.1.2.2 yamt adr r4, mmu_init_table 132 1.1.2.2 yamt b 3f 133 1.1.2.2 yamt 134 1.1.2.2 yamt 2: 135 1.1.2.2 yamt str r3, [r0, r2] 136 1.1.2.2 yamt add r2, r2, #4 137 1.1.2.2 yamt add r3, r3, #(L1_S_SIZE) 138 1.1.2.2 yamt adds r1, r1, #-1 139 1.1.2.2 yamt bhi 2b 140 1.1.2.2 yamt 3: 141 1.1.2.2 yamt ldmia r4!, {r1, r2, r3} /* # of sections, VA, PA|attr */ 142 1.1.2.2 yamt cmp r1, #0 143 1.1.2.2 yamt bne 2b 144 1.1.2.2 yamt 145 1.1.2.2 yamt mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 146 1.1.2.2 yamt mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 147 1.1.2.2 yamt mov r0, #0 148 1.1.2.2 yamt mcr p15, 0, r0, c7, c6, 0 /* Invalidate D cache */ 149 1.1.2.2 yamt mcr p15, 0, r0, c7, c10, 4 /* Drain write-buffer */ 150 1.1.2.2 yamt 151 1.1.2.2 yamt /* Ensure safe Translation Table. */ 152 1.1.2.2 yamt 153 1.1.2.2 yamt /* Set the Domain Access register. Very important! */ 154 1.1.2.2 yamt mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 155 1.1.2.2 yamt mcr p15, 0, r0, c3, c0, 0 156 1.1.2.2 yamt 157 1.1.2.2 yamt /* Enable MMU */ 158 1.1.2.2 yamt mrc p15, 0, r0, c1, c0, 0 159 1.1.2.2 yamt orr r0, r0, #CPU_CONTROL_SYST_ENABLE 160 1.1.2.2 yamt orr r0, r0, #CPU_CONTROL_MMU_ENABLE 161 1.1.2.2 yamt mcr p15, 0, r0, c1, c0, 0 162 1.1.2.2 yamt CPWAIT(r0) 163 1.1.2.2 yamt 164 1.1.2.2 yamt /* Jump to kernel code in TRUE VA */ 165 1.1.2.2 yamt adr r0, Lstart 166 1.1.2.2 yamt ldr pc, [r0] 167 1.1.2.2 yamt 168 1.1.2.2 yamt Lstart: 169 1.1.2.2 yamt .word start 170 1.1.2.2 yamt 171 1.1.2.2 yamt #ifndef STARTUP_PAGETABLE_ADDR 172 1.1.2.2 yamt #define STARTUP_PAGETABLE_ADDR 0x00004000 /* aligned 16kByte */ 173 1.1.2.2 yamt #endif 174 1.1.2.2 yamt Lstartup_pagetable: 175 1.1.2.2 yamt .word STARTUP_PAGETABLE_ADDR 176 1.1.2.2 yamt 177 1.1.2.2 yamt .globl _C_LABEL(u_boot_args) 178 1.1.2.2 yamt u_boot_args: 179 1.1.2.2 yamt .space 16 /* r0, r1, r2, r3 */ 180 1.1.2.2 yamt 181 1.1.2.2 yamt #ifdef CPU_SHEEVA 182 1.1.2.2 yamt sheeva_cores_start: 183 1.1.2.2 yamt .word CPU_ID_MV88SV131 184 1.1.2.2 yamt .word CPU_ID_MV88FR571_VD /* Is it Sheeva? */ 185 1.1.2.2 yamt sheeva_cores_end: 186 1.1.2.2 yamt #endif 187 1.1.2.2 yamt 188 1.1.2.2 yamt #define MMU_INIT(va,pa,n_sec,attr) \ 189 1.1.2.2 yamt .word n_sec ; \ 190 1.1.2.2 yamt .word 4 * ((va) >> L1_S_SHIFT) ; \ 191 1.1.2.2 yamt .word (pa) | (attr) ; 192 1.1.2.2 yamt 193 1.1.2.2 yamt mmu_init_table: 194 1.1.2.2 yamt /* fill all table VA==PA */ 195 1.1.2.2 yamt MMU_INIT(0x00000000, 0x00000000, 196 1.1.2.2 yamt 1 << (32 - L1_S_SHIFT), L1_TYPE_S | L1_S_AP(AP_KRW)) 197 1.1.2.2 yamt 198 1.1.2.2 yamt /* map SDRAM VA==PA, WT cacheable */ 199 1.1.2.2 yamt MMU_INIT(SDRAM_START, SDRAM_START, 200 1.1.2.2 yamt 128, L1_TYPE_S | L1_S_C | L1_S_AP(AP_KRW)) 201 1.1.2.2 yamt 202 1.1.2.2 yamt /* map VA 0xc0000000..0xc7ffffff to PA 0x00000000..0x07ffffff */ 203 1.1.2.2 yamt MMU_INIT(0xc0000000, SDRAM_START, 204 1.1.2.2 yamt 128, L1_TYPE_S | L1_S_C | L1_S_AP(AP_KRW)) 205 1.1.2.2 yamt 206 1.1.2.2 yamt .word 0 /* end of table */ 207
Indexes created Sat Oct 25 16:10:12 GMT 2025