marvell_start.S revision 1.2.2.2
1 1.2.2.2 rmind /* $NetBSD: marvell_start.S,v 1.2.2.2 2011/03/05 20:50:08 rmind Exp $ */ 2 1.2.2.2 rmind /* 3 1.2.2.2 rmind * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation. 4 1.2.2.2 rmind * All rights reserved. 5 1.2.2.2 rmind * 6 1.2.2.2 rmind * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 1.2.2.2 rmind * Corporation. 8 1.2.2.2 rmind * 9 1.2.2.2 rmind * Redistribution and use in source and binary forms, with or without 10 1.2.2.2 rmind * modification, are permitted provided that the following conditions 11 1.2.2.2 rmind * are met: 12 1.2.2.2 rmind * 1. Redistributions of source code must retain the above copyright 13 1.2.2.2 rmind * notice, this list of conditions and the following disclaimer. 14 1.2.2.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 15 1.2.2.2 rmind * notice, this list of conditions and the following disclaimer in the 16 1.2.2.2 rmind * documentation and/or other materials provided with the distribution. 17 1.2.2.2 rmind * 3. Neither the name of the project nor the name of SOUM Corporation 18 1.2.2.2 rmind * may be used to endorse or promote products derived from this software 19 1.2.2.2 rmind * without specific prior written permission. 20 1.2.2.2 rmind * 21 1.2.2.2 rmind * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 1.2.2.2 rmind * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 1.2.2.2 rmind * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 1.2.2.2 rmind * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 1.2.2.2 rmind * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 1.2.2.2 rmind * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 1.2.2.2 rmind * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 1.2.2.2 rmind * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 1.2.2.2 rmind * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 1.2.2.2 rmind * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 1.2.2.2 rmind * POSSIBILITY OF SUCH DAMAGE. 32 1.2.2.2 rmind */ 33 1.2.2.2 rmind /* 34 1.2.2.2 rmind * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 35 1.2.2.2 rmind * Written by Hiroyuki Bessho for Genetec Corporation. 36 1.2.2.2 rmind * 37 1.2.2.2 rmind * Redistribution and use in source and binary forms, with or without 38 1.2.2.2 rmind * modification, are permitted provided that the following conditions 39 1.2.2.2 rmind * are met: 40 1.2.2.2 rmind * 1. Redistributions of source code must retain the above copyright 41 1.2.2.2 rmind * notice, this list of conditions and the following disclaimer. 42 1.2.2.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 43 1.2.2.2 rmind * notice, this list of conditions and the following disclaimer in the 44 1.2.2.2 rmind * documentation and/or other materials provided with the distribution. 45 1.2.2.2 rmind * 3. The name of Genetec Corporation may not be used to endorse or 46 1.2.2.2 rmind * promote products derived from this software without specific prior 47 1.2.2.2 rmind * written permission. 48 1.2.2.2 rmind * 49 1.2.2.2 rmind * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 50 1.2.2.2 rmind * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 1.2.2.2 rmind * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 1.2.2.2 rmind * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 53 1.2.2.2 rmind * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 1.2.2.2 rmind * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 1.2.2.2 rmind * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 1.2.2.2 rmind * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 1.2.2.2 rmind * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 1.2.2.2 rmind * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 1.2.2.2 rmind * POSSIBILITY OF SUCH DAMAGE. 60 1.2.2.2 rmind */ 61 1.2.2.2 rmind 62 1.2.2.2 rmind #include "opt_cputypes.h" 63 1.2.2.2 rmind #include <machine/asm.h> 64 1.2.2.2 rmind #include <arm/armreg.h> 65 1.2.2.2 rmind #include "assym.h" 66 1.2.2.2 rmind 67 1.2.2.2 rmind RCSID("$NetBSD: marvell_start.S,v 1.2.2.2 2011/03/05 20:50:08 rmind Exp $") 68 1.2.2.2 rmind 69 1.2.2.2 rmind #ifndef SDRAM_START 70 1.2.2.2 rmind #define SDRAM_START 0x00000000 71 1.2.2.2 rmind #endif 72 1.2.2.2 rmind 73 1.2.2.2 rmind /* 74 1.2.2.2 rmind * CPWAIT -- Canonical method to wait for CP15 update. 75 1.2.2.2 rmind * NOTE: Clobbers the specified temp reg. 76 1.2.2.2 rmind * copied from arm/arm/cpufunc_asm_xscale.S 77 1.2.2.2 rmind * XXX: better be in a common header file. 78 1.2.2.2 rmind */ 79 1.2.2.2 rmind #define CPWAIT_BRANCH \ 80 1.2.2.2 rmind sub pc, pc, #4 81 1.2.2.2 rmind 82 1.2.2.2 rmind #define CPWAIT(tmp) \ 83 1.2.2.2 rmind mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 84 1.2.2.2 rmind mov tmp, tmp /* wait for it to complete */ ;\ 85 1.2.2.2 rmind CPWAIT_BRANCH /* branch to next insn */ 86 1.2.2.2 rmind 87 1.2.2.2 rmind /* 88 1.2.2.2 rmind * Kernel start routine for Marvell boards 89 1.2.2.2 rmind * this code is excuted at the very first after the kernel is loaded 90 1.2.2.2 rmind * by U-Boot. 91 1.2.2.2 rmind */ 92 1.2.2.2 rmind .text 93 1.2.2.2 rmind 94 1.2.2.2 rmind .global _C_LABEL(marvell_start) 95 1.2.2.2 rmind _C_LABEL(marvell_start): 96 1.2.2.2 rmind /* The Loader for Marvell board is u-boot. it's running on RAM */ 97 1.2.2.2 rmind /* 98 1.2.2.2 rmind * Kernel is loaded in SDRAM (0x00200000..), and is expected to run 99 1.2.2.2 rmind * in VA 0xc0200000.. 100 1.2.2.2 rmind */ 101 1.2.2.2 rmind 102 1.2.2.2 rmind #ifdef CPU_SHEEVA 103 1.2.2.2 rmind mrc p15, 0, r4, c0, c0, 0 104 1.2.2.2 rmind and r4, r4, #CPU_ID_CPU_MASK 105 1.2.2.2 rmind adr r5, sheeva_cores_start 106 1.2.2.2 rmind adr r6, sheeva_cores_end 107 1.2.2.2 rmind 1: 108 1.2.2.2 rmind cmp r5, r6 109 1.2.2.2 rmind beq 2f 110 1.2.2.2 rmind ldmia r5!, {r7} 111 1.2.2.2 rmind cmp r4, r7 112 1.2.2.2 rmind bne 1b 113 1.2.2.2 rmind 114 1.2.2.2 rmind /* Make sure L2 is disabled */ 115 1.2.2.2 rmind mrc p15, 1, r0, c15, c1, 0 @ Get Marvell Extra Features Register 116 1.2.2.2 rmind bic r0, r0, #0x00400000 @ disable L2 cache 117 1.2.2.2 rmind mcr p15, 1, r0, c15, c1, 0 118 1.2.2.2 rmind 2: 119 1.2.2.2 rmind #endif 120 1.2.2.2 rmind /* save u-boot's args */ 121 1.2.2.2 rmind adr r4, u_boot_args 122 1.2.2.2 rmind nop 123 1.2.2.2 rmind nop 124 1.2.2.2 rmind nop 125 1.2.2.2 rmind stmia r4!, {r0, r1, r2, r3} 126 1.2.2.2 rmind nop 127 1.2.2.2 rmind nop 128 1.2.2.2 rmind nop 129 1.2.2.2 rmind 130 1.2.2.2 rmind /* build page table from scratch */ 131 1.2.2.2 rmind ldr r0, Lstartup_pagetable /* pagetable */ 132 1.2.2.2 rmind adr r4, mmu_init_table 133 1.2.2.2 rmind b 3f 134 1.2.2.2 rmind 135 1.2.2.2 rmind 2: 136 1.2.2.2 rmind str r3, [r0, r2] 137 1.2.2.2 rmind add r2, r2, #4 138 1.2.2.2 rmind add r3, r3, #(L1_S_SIZE) 139 1.2.2.2 rmind adds r1, r1, #-1 140 1.2.2.2 rmind bhi 2b 141 1.2.2.2 rmind 3: 142 1.2.2.2 rmind ldmia r4!, {r1, r2, r3} /* # of sections, VA, PA|attr */ 143 1.2.2.2 rmind cmp r1, #0 144 1.2.2.2 rmind bne 2b 145 1.2.2.2 rmind 146 1.2.2.2 rmind mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 147 1.2.2.2 rmind mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 148 1.2.2.2 rmind mov r0, #0 149 1.2.2.2 rmind mcr p15, 0, r0, c7, c6, 0 /* Invalidate D cache */ 150 1.2.2.2 rmind mcr p15, 0, r0, c7, c10, 4 /* Drain write-buffer */ 151 1.2.2.2 rmind 152 1.2.2.2 rmind /* Ensure safe Translation Table. */ 153 1.2.2.2 rmind 154 1.2.2.2 rmind /* Set the Domain Access register. Very important! */ 155 1.2.2.2 rmind mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 156 1.2.2.2 rmind mcr p15, 0, r0, c3, c0, 0 157 1.2.2.2 rmind 158 1.2.2.2 rmind /* Enable MMU */ 159 1.2.2.2 rmind mrc p15, 0, r0, c1, c0, 0 160 1.2.2.2 rmind orr r0, r0, #CPU_CONTROL_SYST_ENABLE 161 1.2.2.2 rmind orr r0, r0, #CPU_CONTROL_MMU_ENABLE 162 1.2.2.2 rmind mcr p15, 0, r0, c1, c0, 0 163 1.2.2.2 rmind CPWAIT(r0) 164 1.2.2.2 rmind 165 1.2.2.2 rmind /* Jump to kernel code in TRUE VA */ 166 1.2.2.2 rmind adr r0, Lstart 167 1.2.2.2 rmind ldr pc, [r0] 168 1.2.2.2 rmind 169 1.2.2.2 rmind Lstart: 170 1.2.2.2 rmind .word start 171 1.2.2.2 rmind 172 1.2.2.2 rmind #ifndef STARTUP_PAGETABLE_ADDR 173 1.2.2.2 rmind #define STARTUP_PAGETABLE_ADDR 0x00004000 /* aligned 16kByte */ 174 1.2.2.2 rmind #endif 175 1.2.2.2 rmind Lstartup_pagetable: 176 1.2.2.2 rmind .word STARTUP_PAGETABLE_ADDR 177 1.2.2.2 rmind 178 1.2.2.2 rmind .globl _C_LABEL(u_boot_args) 179 1.2.2.2 rmind u_boot_args: 180 1.2.2.2 rmind .space 16 /* r0, r1, r2, r3 */ 181 1.2.2.2 rmind 182 1.2.2.2 rmind #ifdef CPU_SHEEVA 183 1.2.2.2 rmind sheeva_cores_start: 184 1.2.2.2 rmind .word CPU_ID_MV88SV131 185 1.2.2.2 rmind .word CPU_ID_MV88FR571_VD /* Is it Sheeva? */ 186 1.2.2.2 rmind sheeva_cores_end: 187 1.2.2.2 rmind #endif 188 1.2.2.2 rmind 189 1.2.2.2 rmind #define MMU_INIT(va,pa,n_sec,attr) \ 190 1.2.2.2 rmind .word n_sec ; \ 191 1.2.2.2 rmind .word 4 * ((va) >> L1_S_SHIFT) ; \ 192 1.2.2.2 rmind .word (pa) | (attr) ; 193 1.2.2.2 rmind 194 1.2.2.2 rmind mmu_init_table: 195 1.2.2.2 rmind /* fill all table VA==PA */ 196 1.2.2.2 rmind MMU_INIT(0x00000000, 0x00000000, 197 1.2.2.2 rmind 1 << (32 - L1_S_SHIFT), L1_TYPE_S | L1_S_AP_KRW) 198 1.2.2.2 rmind 199 1.2.2.2 rmind /* map SDRAM VA==PA, WT cacheable */ 200 1.2.2.2 rmind MMU_INIT(SDRAM_START, SDRAM_START, 201 1.2.2.2 rmind 128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW) 202 1.2.2.2 rmind 203 1.2.2.2 rmind /* map VA 0xc0000000..0xc7ffffff to PA 0x00000000..0x07ffffff */ 204 1.2.2.2 rmind MMU_INIT(0xc0000000, SDRAM_START, 205 1.2.2.2 rmind 128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW) 206 1.2.2.2 rmind 207 1.2.2.2 rmind .word 0 /* end of table */ 208
Indexes created Sat Oct 25 16:10:12 GMT 2025