marvell_start.S revision 1.1
1 /* $NetBSD: marvell_start.S,v 1.1 2010/10/03 06:03:10 kiyohara Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 35 * Written by Hiroyuki Bessho for Genetec Corporation. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. The name of Genetec Corporation may not be used to endorse or 46 * promote products derived from this software without specific prior 47 * written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 #include "opt_cputypes.h" 63 #include <machine/asm.h> 64 #include <arm/armreg.h> 65 #include <arm/arm32/pte.h> 66 #include <arm/arm32/pmap.h> /* for PMAP_DOMAIN_KERNEL */ 67 68 #ifndef SDRAM_START 69 #define SDRAM_START 0x00000000 70 #endif 71 72 /* 73 * CPWAIT -- Canonical method to wait for CP15 update. 74 * NOTE: Clobbers the specified temp reg. 75 * copied from arm/arm/cpufunc_asm_xscale.S 76 * XXX: better be in a common header file. 77 */ 78 #define CPWAIT_BRANCH \ 79 sub pc, pc, #4 80 81 #define CPWAIT(tmp) \ 82 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 83 mov tmp, tmp /* wait for it to complete */ ;\ 84 CPWAIT_BRANCH /* branch to next insn */ 85 86 /* 87 * Kernel start routine for Marvell boards 88 * this code is excuted at the very first after the kernel is loaded 89 * by U-Boot. 90 */ 91 .text 92 93 .global _C_LABEL(marvell_start) 94 _C_LABEL(marvell_start): 95 /* The Loader for Marvell board is u-boot. it's running on RAM */ 96 /* 97 * Kernel is loaded in SDRAM (0x00200000..), and is expected to run 98 * in VA 0xc0200000.. 99 */ 100 101 #ifdef CPU_SHEEVA 102 mrc p15, 0, r4, c0, c0, 0 103 and r4, r4, #CPU_ID_CPU_MASK 104 adr r5, sheeva_cores_start 105 adr r6, sheeva_cores_end 106 1: 107 cmp r5, r6 108 beq 2f 109 ldmia r5!, {r7} 110 cmp r4, r7 111 bne 1b 112 113 /* Make sure L2 is disabled */ 114 mrc p15, 1, r0, c15, c1, 0 @ Get Marvell Extra Features Register 115 bic r0, r0, #0x00400000 @ disable L2 cache 116 mcr p15, 1, r0, c15, c1, 0 117 2: 118 #endif 119 /* save u-boot's args */ 120 adr r4, u_boot_args 121 nop 122 nop 123 nop 124 stmia r4!, {r0, r1, r2, r3} 125 nop 126 nop 127 nop 128 129 /* build page table from scratch */ 130 ldr r0, Lstartup_pagetable /* pagetable */ 131 adr r4, mmu_init_table 132 b 3f 133 134 2: 135 str r3, [r0, r2] 136 add r2, r2, #4 137 add r3, r3, #(L1_S_SIZE) 138 adds r1, r1, #-1 139 bhi 2b 140 3: 141 ldmia r4!, {r1, r2, r3} /* # of sections, VA, PA|attr */ 142 cmp r1, #0 143 bne 2b 144 145 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 146 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 147 mov r0, #0 148 mcr p15, 0, r0, c7, c6, 0 /* Invalidate D cache */ 149 mcr p15, 0, r0, c7, c10, 4 /* Drain write-buffer */ 150 151 /* Ensure safe Translation Table. */ 152 153 /* Set the Domain Access register. Very important! */ 154 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 155 mcr p15, 0, r0, c3, c0, 0 156 157 /* Enable MMU */ 158 mrc p15, 0, r0, c1, c0, 0 159 orr r0, r0, #CPU_CONTROL_SYST_ENABLE 160 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 161 mcr p15, 0, r0, c1, c0, 0 162 CPWAIT(r0) 163 164 /* Jump to kernel code in TRUE VA */ 165 adr r0, Lstart 166 ldr pc, [r0] 167 168 Lstart: 169 .word start 170 171 #ifndef STARTUP_PAGETABLE_ADDR 172 #define STARTUP_PAGETABLE_ADDR 0x00004000 /* aligned 16kByte */ 173 #endif 174 Lstartup_pagetable: 175 .word STARTUP_PAGETABLE_ADDR 176 177 .globl _C_LABEL(u_boot_args) 178 u_boot_args: 179 .space 16 /* r0, r1, r2, r3 */ 180 181 #ifdef CPU_SHEEVA 182 sheeva_cores_start: 183 .word CPU_ID_MV88SV131 184 .word CPU_ID_MV88FR571_VD /* Is it Sheeva? */ 185 sheeva_cores_end: 186 #endif 187 188 #define MMU_INIT(va,pa,n_sec,attr) \ 189 .word n_sec ; \ 190 .word 4 * ((va) >> L1_S_SHIFT) ; \ 191 .word (pa) | (attr) ; 192 193 mmu_init_table: 194 /* fill all table VA==PA */ 195 MMU_INIT(0x00000000, 0x00000000, 196 1 << (32 - L1_S_SHIFT), L1_TYPE_S | L1_S_AP(AP_KRW)) 197 198 /* map SDRAM VA==PA, WT cacheable */ 199 MMU_INIT(SDRAM_START, SDRAM_START, 200 128, L1_TYPE_S | L1_S_C | L1_S_AP(AP_KRW)) 201 202 /* map VA 0xc0000000..0xc7ffffff to PA 0x00000000..0x07ffffff */ 203 MMU_INIT(0xc0000000, SDRAM_START, 204 128, L1_TYPE_S | L1_S_C | L1_S_AP(AP_KRW)) 205 206 .word 0 /* end of table */ 207
Indexes created Thu Oct 02 10:09:58 GMT 2025