marvell_start.S revision 1.1.8.1
1 /* $NetBSD: marvell_start.S,v 1.1.8.1 2011/02/08 16:19:17 bouyer Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 35 * Written by Hiroyuki Bessho for Genetec Corporation. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. The name of Genetec Corporation may not be used to endorse or 46 * promote products derived from this software without specific prior 47 * written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 #include "opt_cputypes.h" 63 #include <machine/asm.h> 64 #include <arm/armreg.h> 65 #include "assym.h" 66 67 RCSID("$NetBSD: marvell_start.S,v 1.1.8.1 2011/02/08 16:19:17 bouyer Exp $") 68 69 #ifndef SDRAM_START 70 #define SDRAM_START 0x00000000 71 #endif 72 73 /* 74 * CPWAIT -- Canonical method to wait for CP15 update. 75 * NOTE: Clobbers the specified temp reg. 76 * copied from arm/arm/cpufunc_asm_xscale.S 77 * XXX: better be in a common header file. 78 */ 79 #define CPWAIT_BRANCH \ 80 sub pc, pc, #4 81 82 #define CPWAIT(tmp) \ 83 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 84 mov tmp, tmp /* wait for it to complete */ ;\ 85 CPWAIT_BRANCH /* branch to next insn */ 86 87 /* 88 * Kernel start routine for Marvell boards 89 * this code is excuted at the very first after the kernel is loaded 90 * by U-Boot. 91 */ 92 .text 93 94 .global _C_LABEL(marvell_start) 95 _C_LABEL(marvell_start): 96 /* The Loader for Marvell board is u-boot. it's running on RAM */ 97 /* 98 * Kernel is loaded in SDRAM (0x00200000..), and is expected to run 99 * in VA 0xc0200000.. 100 */ 101 102 #ifdef CPU_SHEEVA 103 mrc p15, 0, r4, c0, c0, 0 104 and r4, r4, #CPU_ID_CPU_MASK 105 adr r5, sheeva_cores_start 106 adr r6, sheeva_cores_end 107 1: 108 cmp r5, r6 109 beq 2f 110 ldmia r5!, {r7} 111 cmp r4, r7 112 bne 1b 113 114 /* Make sure L2 is disabled */ 115 mrc p15, 1, r0, c15, c1, 0 @ Get Marvell Extra Features Register 116 bic r0, r0, #0x00400000 @ disable L2 cache 117 mcr p15, 1, r0, c15, c1, 0 118 2: 119 #endif 120 /* save u-boot's args */ 121 adr r4, u_boot_args 122 nop 123 nop 124 nop 125 stmia r4!, {r0, r1, r2, r3} 126 nop 127 nop 128 nop 129 130 /* build page table from scratch */ 131 ldr r0, Lstartup_pagetable /* pagetable */ 132 adr r4, mmu_init_table 133 b 3f 134 135 2: 136 str r3, [r0, r2] 137 add r2, r2, #4 138 add r3, r3, #(L1_S_SIZE) 139 adds r1, r1, #-1 140 bhi 2b 141 3: 142 ldmia r4!, {r1, r2, r3} /* # of sections, VA, PA|attr */ 143 cmp r1, #0 144 bne 2b 145 146 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 147 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 148 mov r0, #0 149 mcr p15, 0, r0, c7, c6, 0 /* Invalidate D cache */ 150 mcr p15, 0, r0, c7, c10, 4 /* Drain write-buffer */ 151 152 /* Ensure safe Translation Table. */ 153 154 /* Set the Domain Access register. Very important! */ 155 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 156 mcr p15, 0, r0, c3, c0, 0 157 158 /* Enable MMU */ 159 mrc p15, 0, r0, c1, c0, 0 160 orr r0, r0, #CPU_CONTROL_SYST_ENABLE 161 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 162 mcr p15, 0, r0, c1, c0, 0 163 CPWAIT(r0) 164 165 /* Jump to kernel code in TRUE VA */ 166 adr r0, Lstart 167 ldr pc, [r0] 168 169 Lstart: 170 .word start 171 172 #ifndef STARTUP_PAGETABLE_ADDR 173 #define STARTUP_PAGETABLE_ADDR 0x00004000 /* aligned 16kByte */ 174 #endif 175 Lstartup_pagetable: 176 .word STARTUP_PAGETABLE_ADDR 177 178 .globl _C_LABEL(u_boot_args) 179 u_boot_args: 180 .space 16 /* r0, r1, r2, r3 */ 181 182 #ifdef CPU_SHEEVA 183 sheeva_cores_start: 184 .word CPU_ID_MV88SV131 185 .word CPU_ID_MV88FR571_VD /* Is it Sheeva? */ 186 sheeva_cores_end: 187 #endif 188 189 #define MMU_INIT(va,pa,n_sec,attr) \ 190 .word n_sec ; \ 191 .word 4 * ((va) >> L1_S_SHIFT) ; \ 192 .word (pa) | (attr) ; 193 194 mmu_init_table: 195 /* fill all table VA==PA */ 196 MMU_INIT(0x00000000, 0x00000000, 197 1 << (32 - L1_S_SHIFT), L1_TYPE_S | L1_S_AP_KRW) 198 199 /* map SDRAM VA==PA, WT cacheable */ 200 MMU_INIT(SDRAM_START, SDRAM_START, 201 128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW) 202 203 /* map VA 0xc0000000..0xc7ffffff to PA 0x00000000..0x07ffffff */ 204 MMU_INIT(0xc0000000, SDRAM_START, 205 128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW) 206 207 .word 0 /* end of table */ 208
Indexes created Wed Oct 22 13:09:56 GMT 2025