marvell_start.S revision 1.11
1 /* $NetBSD: marvell_start.S,v 1.11 2021/08/30 00:00:02 rin Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 35 * Written by Hiroyuki Bessho for Genetec Corporation. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. The name of Genetec Corporation may not be used to endorse or 46 * promote products derived from this software without specific prior 47 * written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 #include "opt_cputypes.h" 63 #include "opt_mvsoc.h" 64 #include <machine/asm.h> 65 #include <arm/armreg.h> 66 #include <evbarm/marvell/marvellreg.h> 67 #include "assym.h" 68 69 RCSID("$NetBSD: marvell_start.S,v 1.11 2021/08/30 00:00:02 rin Exp $") 70 71 #ifndef SDRAM_START 72 #define SDRAM_START 0x00000000 73 #endif 74 75 #define SHEEVA 1 76 #define PJ4B 2 77 78 /* 79 * CPWAIT -- Canonical method to wait for CP15 update. 80 * NOTE: Clobbers the specified temp reg. 81 * copied from arm/arm/cpufunc_asm_xscale.S 82 * XXX: better be in a common header file. 83 */ 84 #define CPWAIT_BRANCH \ 85 sub pc, pc, #4 86 87 #define CPWAIT(tmp) \ 88 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 89 mov tmp, tmp /* wait for it to complete */ ;\ 90 CPWAIT_BRANCH /* branch to next insn */ 91 92 /* 93 * Kernel start routine for Marvell boards 94 * this code is excuted at the very first after the kernel is loaded 95 * by U-Boot. 96 */ 97 .text 98 99 .global _C_LABEL(marvell_start) 100 _C_LABEL(marvell_start): 101 /* The Loader for Marvell board is u-boot. it's running on RAM */ 102 /* 103 * Kernel is loaded in SDRAM (0x00200000..), and is expected to run 104 * in VA 0xc0200000.. 105 */ 106 107 #ifdef __ARMEB__ 108 /* 109 * u-boot is running in little-endian mode. Therefore, we need to 110 * encode first few instructions in the opposite byte order. 111 */ 112 113 /* Turn on CPU_CONTROL_BEND_ENABLE bit. */ 114 .word 0x104f11ee /* mrc p15, 0, r4, c1, c0, 0 */ 115 .word 0x804084e3 /* orr r4, r4, #CPU_CONTROL_BEND_ENABLE */ 116 .word 0x104f01ee /* mcr p15, 0, r4, c1, c0, 0 */ 117 118 /* Flush prefetch buffer. */ 119 .word 0x0000a0e1 /* nop */ 120 .word 0x0000a0e1 /* nop */ 121 .word 0x0000a0e1 /* nop */ 122 123 CPWAIT(r4) 124 #endif 125 126 /* Check cores */ 127 mrc p15, 0, r4, c0, c0, 0 128 and r4, r4, #CPU_ID_CPU_MASK 129 adr r5, cores_start 130 adr r6, cores_end 131 0: 132 cmp r5, r6 133 beq 1f 134 ldmia r5!, {r7, r8} 135 cmp r4, r7 136 bne 0b 137 138 cmp r8, #SHEEVA 139 bne 1f 140 141 sheeva_l2_disable: 142 /* Make sure L2 is disabled */ 143 mrc p15, 1, r5, c15, c1, 0 @ Get Marvell Extra Features Register 144 bic r5, r5, #0x00400000 @ disable L2 cache 145 mcr p15, 1, r5, c15, c1, 0 146 147 #ifdef SHEEVA_L2_CACHE_WT 148 /* L2 WT Mode */ 149 ldr r5, =0xf1020128 /* CPU L2 Configuration Register */ 150 ldr r6, [r5] 151 bic r6, r6, #0x10 /* Force Write Through */ 152 str r6, [r5] 153 #endif 154 155 1: 156 157 /* save u-boot's args */ 158 adr r4, u_boot_args 159 nop 160 nop 161 nop 162 stmia r4!, {r0, r1, r2, r3} 163 nop 164 nop 165 nop 166 167 #if defined(MVSOC_FIXUP_DEVID) && MVSOC_FIXUP_DEVID > 0 168 adr r6, marvell_interregs_pbase 169 ldr r7, [r6] 170 add r7, r7, #0x40000 171 ldr r6, [r7] 172 bic r6, r6, 0xff000000 173 bic r6, r6, 0x00ff0000 174 /* 175 * Some SoC returns ugly DeviceID. Fixup it. 176 */ 177 adr r5, devid 178 ldr r5, [r5] 179 orr r6, r6, r5, lsl #16 180 str r6, [r7] 181 b 1f 182 devid: 183 .word MVSOC_FIXUP_DEVID 184 marvell_interregs_pbase: 185 .word MARVELL_INTERREGS_PBASE 186 #endif 187 1: 188 189 /* build page table from scratch */ 190 ldr r0, Lstartup_pagetable /* pagetable */ 191 adr r4, mmu_init_table 192 b 3f 193 194 2: 195 str r3, [r0, r2] 196 add r2, r2, #4 197 add r3, r3, #(L1_S_SIZE) 198 adds r1, r1, #-1 199 bhi 2b 200 3: 201 ldmia r4!, {r1, r2, r3} /* # of sections, VA, PA|attr */ 202 cmp r1, #0 203 bne 2b 204 205 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 206 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 207 cmp r8, #PJ4B 208 mcreq p15, 0, r0, c2, c0, 1 /* Set TTB1 */ 209 moveq r1, #TTBCR_S_N_1 210 mcreq p15, 0, r1, c2, c0, 2 /* Set TTBCR */ 211 mov r0, #0 212 mcreq p15, 0, r0, c8, c7, 0 /* Flush TLB */ 213 214 mcreq p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ 215 mcr p15, 0, r0, c7, c6, 0 /* Invalidate D cache */ 216 mcr p15, 0, r0, c7, c10, 4 /* Drain write-buffer */ 217 218 /* Ensure safe Translation Table. */ 219 220 /* Set the Domain Access register. Very important! */ 221 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 222 mcr p15, 0, r0, c3, c0, 0 223 224 /* Enable MMU */ 225 mrc p15, 0, r0, c1, c0, 0 226 cmp r8, #PJ4B 227 orreq r0, r0, #CPU_CONTROL_XP_ENABLE 228 biceq r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE) 229 biceq r0, r0, #(CPU_CONTROL_IC_ENABLE) 230 biceq r0, r0, #(CPU_CONTROL_BPRD_ENABLE) 231 orr r0, r0, #CPU_CONTROL_SYST_ENABLE 232 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 233 mcr p15, 0, r0, c1, c0, 0 234 CPWAIT(r0) 235 236 /* Jump to kernel code in TRUE VA */ 237 adr r0, Lstart 238 ldr pc, [r0] 239 240 Lstart: 241 .word start 242 243 #ifndef STARTUP_PAGETABLE_ADDR 244 #define STARTUP_PAGETABLE_ADDR 0x00004000 /* aligned 16kByte */ 245 #endif 246 Lstartup_pagetable: 247 .word STARTUP_PAGETABLE_ADDR 248 249 .globl _C_LABEL(u_boot_args) 250 u_boot_args: 251 .space 16 /* r0, r1, r2, r3 */ 252 253 cores_start: 254 .word CPU_ID_MV88SV131, SHEEVA 255 .word CPU_ID_MV88FR571_VD, SHEEVA /* Is it Sheeva? */ 256 .word CPU_ID_MV88SV581X_V6, PJ4B 257 .word CPU_ID_MV88SV581X_V7, PJ4B 258 .word CPU_ID_MV88SV584X_V7, PJ4B 259 .word CPU_ID_ARM_88SV581X_V6, PJ4B 260 .word CPU_ID_ARM_88SV581X_V7, PJ4B 261 .word 0, 0 262 cores_end: 263 264 #define MMU_INIT(va,pa,n_sec,attr) \ 265 .word n_sec ; \ 266 .word 4 * (((va) & 0xffffffff) >> L1_S_SHIFT) ; \ 267 .word ((pa) & 0xffffffff) | (attr) ; 268 269 mmu_init_table: 270 /* fill all table VA==PA */ 271 MMU_INIT(0x00000000, 0x00000000, 272 1 << (32 - L1_S_SHIFT), L1_TYPE_S | L1_S_AP_KRW) 273 274 /* map SDRAM VA==PA, WT cacheable */ 275 MMU_INIT(SDRAM_START, SDRAM_START, 276 128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW) 277 278 /* map VA KERNEL_BASE..KERNEL_BASE+7ffffff to PA 0x00000000..0x07ffffff */ 279 MMU_INIT(KERNEL_BASE, SDRAM_START, 280 128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW) 281 282 .word 0 /* end of table */ 283
Indexes created Thu Oct 02 14:10:14 GMT 2025