marvell_start.S revision 1.3
1 /* $NetBSD: marvell_start.S,v 1.3 2013/09/30 12:54:59 kiyohara Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 35 * Written by Hiroyuki Bessho for Genetec Corporation. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. The name of Genetec Corporation may not be used to endorse or 46 * promote products derived from this software without specific prior 47 * written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 #include "opt_cputypes.h" 63 #include "opt_mvsoc.h" 64 #include <machine/asm.h> 65 #include <arm/armreg.h> 66 #include "assym.h" 67 68 RCSID("$NetBSD: marvell_start.S,v 1.3 2013/09/30 12:54:59 kiyohara Exp $") 69 70 #ifndef SDRAM_START 71 #define SDRAM_START 0x00000000 72 #endif 73 74 #define SHEEVA 1 75 #define PJ4B 2 76 77 /* 78 * CPWAIT -- Canonical method to wait for CP15 update. 79 * NOTE: Clobbers the specified temp reg. 80 * copied from arm/arm/cpufunc_asm_xscale.S 81 * XXX: better be in a common header file. 82 */ 83 #define CPWAIT_BRANCH \ 84 sub pc, pc, #4 85 86 #define CPWAIT(tmp) \ 87 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 88 mov tmp, tmp /* wait for it to complete */ ;\ 89 CPWAIT_BRANCH /* branch to next insn */ 90 91 /* 92 * Kernel start routine for Marvell boards 93 * this code is excuted at the very first after the kernel is loaded 94 * by U-Boot. 95 */ 96 .text 97 98 .global _C_LABEL(marvell_start) 99 _C_LABEL(marvell_start): 100 /* The Loader for Marvell board is u-boot. it's running on RAM */ 101 /* 102 * Kernel is loaded in SDRAM (0x00200000..), and is expected to run 103 * in VA 0xc0200000.. 104 */ 105 106 /* Check cores */ 107 mrc p15, 0, r4, c0, c0, 0 108 and r4, r4, #CPU_ID_CPU_MASK 109 adr r5, cores_start 110 adr r6, cores_end 111 0: 112 cmp r5, r6 113 beq 1f 114 ldmia r5!, {r7, r8} 115 cmp r4, r7 116 bne 0b 117 118 cmp r8, #SHEEVA 119 bne 1f 120 121 sheeva_l2_disable: 122 /* Make sure L2 is disabled */ 123 mrc p15, 1, r5, c15, c1, 0 @ Get Marvell Extra Features Register 124 bic r5, r5, #0x00400000 @ disable L2 cache 125 mcr p15, 1, r5, c15, c1, 0 126 1: 127 128 /* save u-boot's args */ 129 adr r4, u_boot_args 130 nop 131 nop 132 nop 133 stmia r4!, {r0, r1, r2, r3} 134 nop 135 nop 136 nop 137 138 /* Check SoC mapped address */ 139 mov r4, #0x1100 140 orr r4, r4, #0x00ab /* Marvell Vendor ID (0x11ab) */ 141 adr r5, marvell_interregs_pbase_list_start 142 adr r6, marvell_interregs_pbase_list_end 143 0: 144 cmp r5, r6 145 beq 1f 146 ldmia r5!, {r7} 147 add r8, r7, #0x40000 148 ldr r8, [r8] /* Read vend/prod reg from PCI config */ 149 bic r8, r8, #0xff000000 150 bic r8, r8, #0x00ff0000 151 cmp r4, r8 152 bne 0b 153 adr r6, marvell_interregs_pbase 154 str r7, [r6] 155 #if defined(MVSOC_FIXUP_DEVID) && MVSOC_FIXUP_DEVID > 0 156 /* 157 * Some SoC returns ugly DeviceID. Fixup it. 158 */ 159 adr r5, devid 160 ldr r5, [r5] 161 orr r8, r8, r5, lsl #16 162 add r7, r7, #0x40000 163 str r8, [r7] 164 b 1f 165 devid: 166 .word MVSOC_FIXUP_DEVID 167 #endif 168 1: 169 170 /* build page table from scratch */ 171 ldr r0, Lstartup_pagetable /* pagetable */ 172 adr r4, mmu_init_table 173 b 3f 174 175 2: 176 str r3, [r0, r2] 177 add r2, r2, #4 178 add r3, r3, #(L1_S_SIZE) 179 adds r1, r1, #-1 180 bhi 2b 181 3: 182 ldmia r4!, {r1, r2, r3} /* # of sections, VA, PA|attr */ 183 cmp r1, #0 184 bne 2b 185 186 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 187 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 188 mov r0, #0 189 cmp r8, #PJ4B 190 mcreq p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ 191 mcr p15, 0, r0, c7, c6, 0 /* Invalidate D cache */ 192 mcr p15, 0, r0, c7, c10, 4 /* Drain write-buffer */ 193 194 /* Ensure safe Translation Table. */ 195 196 /* Set the Domain Access register. Very important! */ 197 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 198 mcr p15, 0, r0, c3, c0, 0 199 200 /* Enable MMU */ 201 mrc p15, 0, r0, c1, c0, 0 202 cmp r8, #PJ4B 203 orreq r0, r0, #CPU_CONTROL_XP_ENABLE 204 biceq r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE) 205 biceq r0, r0, #(CPU_CONTROL_IC_ENABLE) 206 biceq r0, r0, #(CPU_CONTROL_BPRD_ENABLE) 207 orr r0, r0, #CPU_CONTROL_SYST_ENABLE 208 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 209 mcr p15, 0, r0, c1, c0, 0 210 CPWAIT(r0) 211 212 /* Jump to kernel code in TRUE VA */ 213 adr r0, Lstart 214 ldr pc, [r0] 215 216 Lstart: 217 .word start 218 219 #ifndef STARTUP_PAGETABLE_ADDR 220 #define STARTUP_PAGETABLE_ADDR 0x00004000 /* aligned 16kByte */ 221 #endif 222 Lstartup_pagetable: 223 .word STARTUP_PAGETABLE_ADDR 224 225 .globl _C_LABEL(u_boot_args) 226 u_boot_args: 227 .space 16 /* r0, r1, r2, r3 */ 228 229 cores_start: 230 .word CPU_ID_MV88SV131, SHEEVA 231 .word CPU_ID_MV88FR571_VD, SHEEVA /* Is it Sheeva? */ 232 .word CPU_ID_MVOLD, SHEEVA /* Is it Sheeva? */ 233 .word CPU_ID_MV88SV581X_V6, PJ4B 234 .word CPU_ID_MV88SV581X_V7, PJ4B 235 .word CPU_ID_MV88SV584X_V7, PJ4B 236 .word CPU_ID_ARM_88SV581X_V6, PJ4B 237 .word CPU_ID_ARM_88SV581X_V7, PJ4B 238 .word 0, 0 239 cores_end: 240 241 .globl _C_LABEL(marvell_interregs_pbase) 242 marvell_interregs_pbase: 243 .word 0x00000000 244 marvell_interregs_pbase_list_start: 245 .word 0xd0000000 246 .word 0xf1000000 247 marvell_interregs_pbase_list_end: 248 249 #define MMU_INIT(va,pa,n_sec,attr) \ 250 .word n_sec ; \ 251 .word 4 * ((va) >> L1_S_SHIFT) ; \ 252 .word (pa) | (attr) ; 253 254 mmu_init_table: 255 /* fill all table VA==PA */ 256 MMU_INIT(0x00000000, 0x00000000, 257 1 << (32 - L1_S_SHIFT), L1_TYPE_S | L1_S_AP_KRW) 258 259 /* map SDRAM VA==PA, WT cacheable */ 260 MMU_INIT(SDRAM_START, SDRAM_START, 261 128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW) 262 263 /* map VA 0xc0000000..0xc7ffffff to PA 0x00000000..0x07ffffff */ 264 MMU_INIT(0xc0000000, SDRAM_START, 265 128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW) 266 267 .word 0 /* end of table */ 268
Indexes created Thu Oct 02 14:10:14 GMT 2025