marvell_start.S revision 1.9
1 /* $NetBSD: marvell_start.S,v 1.9 2018/10/15 16:54:55 skrll Exp $ */ 2 /* 3 * Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation. 4 * All rights reserved. 5 * 6 * Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM 7 * Corporation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the project nor the name of SOUM Corporation 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS'' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved. 35 * Written by Hiroyuki Bessho for Genetec Corporation. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. The name of Genetec Corporation may not be used to endorse or 46 * promote products derived from this software without specific prior 47 * written permission. 48 * 49 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 50 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 #include "opt_cputypes.h" 63 #include "opt_mvsoc.h" 64 #include <machine/asm.h> 65 #include <arm/armreg.h> 66 #include <evbarm/marvell/marvellreg.h> 67 #include "assym.h" 68 69 RCSID("$NetBSD: marvell_start.S,v 1.9 2018/10/15 16:54:55 skrll Exp $") 70 71 #ifndef SDRAM_START 72 #define SDRAM_START 0x00000000 73 #endif 74 75 #define SHEEVA 1 76 #define PJ4B 2 77 78 /* 79 * CPWAIT -- Canonical method to wait for CP15 update. 80 * NOTE: Clobbers the specified temp reg. 81 * copied from arm/arm/cpufunc_asm_xscale.S 82 * XXX: better be in a common header file. 83 */ 84 #define CPWAIT_BRANCH \ 85 sub pc, pc, #4 86 87 #define CPWAIT(tmp) \ 88 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\ 89 mov tmp, tmp /* wait for it to complete */ ;\ 90 CPWAIT_BRANCH /* branch to next insn */ 91 92 /* 93 * Kernel start routine for Marvell boards 94 * this code is excuted at the very first after the kernel is loaded 95 * by U-Boot. 96 */ 97 .text 98 99 .global _C_LABEL(marvell_start) 100 _C_LABEL(marvell_start): 101 /* The Loader for Marvell board is u-boot. it's running on RAM */ 102 /* 103 * Kernel is loaded in SDRAM (0x00200000..), and is expected to run 104 * in VA 0xc0200000.. 105 */ 106 107 /* Check cores */ 108 mrc p15, 0, r4, c0, c0, 0 109 and r4, r4, #CPU_ID_CPU_MASK 110 adr r5, cores_start 111 adr r6, cores_end 112 0: 113 cmp r5, r6 114 beq 1f 115 ldmia r5!, {r7, r8} 116 cmp r4, r7 117 bne 0b 118 119 cmp r8, #SHEEVA 120 bne 1f 121 122 sheeva_l2_disable: 123 /* Make sure L2 is disabled */ 124 mrc p15, 1, r5, c15, c1, 0 @ Get Marvell Extra Features Register 125 bic r5, r5, #0x00400000 @ disable L2 cache 126 mcr p15, 1, r5, c15, c1, 0 127 128 #ifdef SHEEVA_L2_CACHE_WT 129 /* L2 WT Mode */ 130 ldr r5, =0xf1020128 /* CPU L2 Configuration Register */ 131 ldr r6, [r5] 132 bic r6, r6, #0x10 /* Force Write Through */ 133 str r6, [r5] 134 #endif 135 136 1: 137 138 /* save u-boot's args */ 139 adr r4, u_boot_args 140 nop 141 nop 142 nop 143 stmia r4!, {r0, r1, r2, r3} 144 nop 145 nop 146 nop 147 148 #if defined(MVSOC_FIXUP_DEVID) && MVSOC_FIXUP_DEVID > 0 149 adr r6, marvell_interregs_pbase 150 ldr r7, [r6] 151 add r7, r7, #0x40000 152 ldr r6, [r7] 153 bic r6, r6, 0xff000000 154 bic r6, r6, 0x00ff0000 155 /* 156 * Some SoC returns ugly DeviceID. Fixup it. 157 */ 158 adr r5, devid 159 ldr r5, [r5] 160 orr r6, r6, r5, lsl #16 161 str r6, [r7] 162 b 1f 163 devid: 164 .word MVSOC_FIXUP_DEVID 165 marvell_interregs_pbase: 166 .word MARVELL_INTERREGS_PBASE 167 #endif 168 1: 169 170 /* build page table from scratch */ 171 ldr r0, Lstartup_pagetable /* pagetable */ 172 adr r4, mmu_init_table 173 b 3f 174 175 2: 176 str r3, [r0, r2] 177 add r2, r2, #4 178 add r3, r3, #(L1_S_SIZE) 179 adds r1, r1, #-1 180 bhi 2b 181 3: 182 ldmia r4!, {r1, r2, r3} /* # of sections, VA, PA|attr */ 183 cmp r1, #0 184 bne 2b 185 186 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 187 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 188 cmp r8, #PJ4B 189 mcreq p15, 0, r0, c2, c0, 1 /* Set TTB1 */ 190 moveq r1, #TTBCR_S_N_1 191 mcreq p15, 0, r1, c2, c0, 2 /* Set TTBCR */ 192 mov r0, #0 193 mcreq p15, 0, r0, c8, c7, 0 /* Flush TLB */ 194 195 mcreq p15, 0, r0, c13, c0, 1 /* Set ASID to 0 */ 196 mcr p15, 0, r0, c7, c6, 0 /* Invalidate D cache */ 197 mcr p15, 0, r0, c7, c10, 4 /* Drain write-buffer */ 198 199 /* Ensure safe Translation Table. */ 200 201 /* Set the Domain Access register. Very important! */ 202 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT) 203 mcr p15, 0, r0, c3, c0, 0 204 205 /* Enable MMU */ 206 mrc p15, 0, r0, c1, c0, 0 207 cmp r8, #PJ4B 208 orreq r0, r0, #CPU_CONTROL_XP_ENABLE 209 biceq r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE | CPU_CONTROL_WBUF_ENABLE) 210 biceq r0, r0, #(CPU_CONTROL_IC_ENABLE) 211 biceq r0, r0, #(CPU_CONTROL_BPRD_ENABLE) 212 orr r0, r0, #CPU_CONTROL_SYST_ENABLE 213 orr r0, r0, #CPU_CONTROL_MMU_ENABLE 214 mcr p15, 0, r0, c1, c0, 0 215 CPWAIT(r0) 216 217 /* Jump to kernel code in TRUE VA */ 218 adr r0, Lstart 219 ldr pc, [r0] 220 221 Lstart: 222 .word start 223 224 #ifndef STARTUP_PAGETABLE_ADDR 225 #define STARTUP_PAGETABLE_ADDR 0x00004000 /* aligned 16kByte */ 226 #endif 227 Lstartup_pagetable: 228 .word STARTUP_PAGETABLE_ADDR 229 230 .globl _C_LABEL(u_boot_args) 231 u_boot_args: 232 .space 16 /* r0, r1, r2, r3 */ 233 234 cores_start: 235 .word CPU_ID_MV88SV131, SHEEVA 236 .word CPU_ID_MV88FR571_VD, SHEEVA /* Is it Sheeva? */ 237 .word CPU_ID_MV88SV581X_V6, PJ4B 238 .word CPU_ID_MV88SV581X_V7, PJ4B 239 .word CPU_ID_MV88SV584X_V7, PJ4B 240 .word CPU_ID_ARM_88SV581X_V6, PJ4B 241 .word CPU_ID_ARM_88SV581X_V7, PJ4B 242 .word 0, 0 243 cores_end: 244 245 #define MMU_INIT(va,pa,n_sec,attr) \ 246 .word n_sec ; \ 247 .word 4 * ((va) >> L1_S_SHIFT) ; \ 248 .word (pa) | (attr) ; 249 250 mmu_init_table: 251 /* fill all table VA==PA */ 252 MMU_INIT(0x00000000, 0x00000000, 253 1 << (32 - L1_S_SHIFT), L1_TYPE_S | L1_S_AP_KRW) 254 255 /* map SDRAM VA==PA, WT cacheable */ 256 MMU_INIT(SDRAM_START, SDRAM_START, 257 128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW) 258 259 /* map VA KERNEL_BASE..KERNEL_BASE+7ffffff to PA 0x00000000..0x07ffffff */ 260 MMU_INIT(KERNEL_BASE, SDRAM_START, 261 128, L1_TYPE_S | L1_S_C | L1_S_AP_KRW) 262 263 .word 0 /* end of table */ 264
Indexes created Thu Oct 02 10:09:58 GMT 2025