1 /* $NetBSD: nslu2_pci.c,v 1.8 2018/11/18 14:25:17 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Copyright (c) 2003 33 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 45 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 47 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 48 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 49 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 #include <sys/cdefs.h> 59 __KERNEL_RCSID(0, "$NetBSD: nslu2_pci.c,v 1.8 2018/11/18 14:25:17 jmcneill Exp $"); 60 61 /* 62 * Linksys NSLU2 PCI support. 63 */ 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/device.h> 68 69 #include <arm/xscale/ixp425reg.h> 70 #include <arm/xscale/ixp425var.h> 71 72 #include <dev/pci/pcivar.h> 73 74 #include <evbarm/nslu2/nslu2reg.h> 75 76 static int 77 nslu2_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 78 { 79 80 KASSERT(pa->pa_bus == 0 && pa->pa_device == 1); 81 82 switch (pa->pa_function) { 83 case 0: 84 *ihp = PCI_INT_A; 85 break; 86 87 case 1: 88 *ihp = PCI_INT_B; 89 break; 90 91 case 2: 92 *ihp = PCI_INT_C; 93 break; 94 95 default: 96 return (1); 97 } 98 99 return (0); 100 } 101 102 static const char * 103 nslu2_pci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 104 { 105 char c; 106 switch (ih) { 107 case PCI_INT_A: 108 c = 'A'; 109 break; 110 111 case PCI_INT_B: 112 c = 'B'; 113 break; 114 115 case PCI_INT_C: 116 c = 'C'; 117 break; 118 default: 119 c = '?'; 120 } 121 snprintf(buf, len, "PCI%c", c); 122 123 return buf; 124 } 125 126 static const struct evcnt * 127 nslu2_pci_intr_evcnt(void *v, pci_intr_handle_t ih) 128 { 129 130 return (NULL); 131 } 132 133 static void * 134 nslu2_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 135 int (*func)(void *), void *arg, const char *xname) 136 { 137 138 return (ixp425_intr_establish(ih, ipl, func, arg)); 139 } 140 141 static void 142 nslu2_pci_intr_disestablish(void *v, void *cookie) 143 { 144 145 ixp425_intr_disestablish(cookie); 146 } 147 148 void 149 ixp425_md_pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, 150 int swiz, int *ilinep) 151 { 152 153 KASSERT(bus == 0 && dev == 1); 154 155 *ilinep = ((swiz + pin - 1) & 3); 156 } 157 158 void 159 ixp425_md_pci_init(struct ixp425_softc *sc) 160 { 161 pci_chipset_tag_t pc = &sc->ia_pci_chipset; 162 uint32_t reg; 163 164 pc->pc_intr_v = sc; 165 pc->pc_intr_map = nslu2_pci_intr_map; 166 pc->pc_intr_string = nslu2_pci_intr_string; 167 pc->pc_intr_evcnt = nslu2_pci_intr_evcnt; 168 pc->pc_intr_establish = nslu2_pci_intr_establish; 169 pc->pc_intr_disestablish = nslu2_pci_intr_disestablish; 170 171 /* PCI Reset Assert */ 172 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR); 173 reg &= ~(1u << GPIO_PCI_RESET); 174 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg); 175 176 /* PCI Clock Disable */ 177 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR); 178 reg &= ~GPCLKR_MUX14; 179 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg); 180 181 /* 182 * Set GPIO Direction 183 * Output: PCI_CLK, PCI_RESET 184 * Input: PCI_INTA, PCI_INTB, PCI_INTC 185 */ 186 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER); 187 reg &= ~((1u << GPIO_PCI_CLK) | (1u << GPIO_PCI_RESET)); 188 reg |= (1u << GPIO_PCI_INTA) | (1u << GPIO_PCI_INTB) | 189 (1u << GPIO_PCI_INTC); 190 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER, reg); 191 192 /* 193 * Set GPIO interrupt type 194 * PCI_INT_A, PCI_INTB, PCI_INT_C: Active Low 195 */ 196 reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA)); 197 reg &= ~GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_MASK); 198 reg |= GPIO_TYPE(GPIO_PCI_INTA, GPIO_TYPE_ACT_LOW); 199 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTA), reg); 200 201 reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB)); 202 reg &= ~GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_MASK); 203 reg |= GPIO_TYPE(GPIO_PCI_INTB, GPIO_TYPE_ACT_LOW); 204 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTB), reg); 205 206 reg = GPIO_CONF_READ_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC)); 207 reg &= ~GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_MASK); 208 reg |= GPIO_TYPE(GPIO_PCI_INTC, GPIO_TYPE_ACT_LOW); 209 GPIO_CONF_WRITE_4(sc, GPIO_TYPE_REG(GPIO_PCI_INTC), reg); 210 211 /* Clear ISR */ 212 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPISR, (1u << GPIO_PCI_INTA) | 213 (1u << GPIO_PCI_INTB) | (1u << GPIO_PCI_INTC)); 214 215 /* Wait 1ms to satisfy "minimum reset assertion time" of the PCI spec */ 216 DELAY(1000); 217 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR); 218 reg |= (0xf << GPCLKR_CLK0DC_SHIFT) | (0xf << GPCLKR_CLK0TC_SHIFT); 219 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg); 220 221 /* PCI Clock Enable */ 222 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPCLKR); 223 reg |= GPCLKR_MUX14; 224 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPCLKR, reg); 225 226 /* 227 * Wait 100us to satisfy "minimum reset assertion time from clock stable 228 * requirement of the PCI spec 229 */ 230 DELAY(100); 231 /* PCI Reset deassert */ 232 reg = GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOUTR); 233 reg |= 1u << GPIO_PCI_RESET; 234 GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOUTR, reg); 235 236 /* 237 * AHB->PCI address translation 238 * PCI Memory Map allocation in 0x48000000 (64MB) 239 * see. IXP425_PCI_MEM_HWBASE 240 */ 241 PCI_CSR_WRITE_4(sc, PCI_PCIMEMBASE, 0x48494a4b); 242 243 /* 244 * PCI->AHB address translation 245 * begin at the physical memory start + OFFSET 246 */ 247 #define AHB_OFFSET 0x10000000UL 248 reg = (AHB_OFFSET + 0x00000000) >> 0; 249 reg |= (AHB_OFFSET + 0x01000000) >> 8; 250 reg |= (AHB_OFFSET + 0x02000000) >> 16; 251 reg |= (AHB_OFFSET + 0x03000000) >> 24; 252 PCI_CSR_WRITE_4(sc, PCI_AHBMEMBASE, reg); 253 254 /* Write Mapping registers PCI Configuration Registers */ 255 /* Base Address 0 - 3 */ 256 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR0, AHB_OFFSET + 0x00000000); 257 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR1, AHB_OFFSET + 0x01000000); 258 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR2, AHB_OFFSET + 0x02000000); 259 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR3, AHB_OFFSET + 0x03000000); 260 261 /* Base Address 4 */ 262 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR4, 0xffffffff); 263 264 /* Base Address 5 */ 265 ixp425_pci_conf_reg_write(sc, PCI_MAPREG_BAR5, 0x00000000); 266 267 /* Assert some PCI errors */ 268 PCI_CSR_WRITE_4(sc, PCI_ISR, ISR_AHBE | ISR_PPE | ISR_PFE | ISR_PSE); 269 270 /* 271 * Set up byte lane swapping between little-endian PCI 272 * and the big-endian AHB bus 273 */ 274 PCI_CSR_WRITE_4(sc, PCI_CSR, CSR_IC | CSR_ABE | CSR_PDS); 275 276 /* 277 * Enable bus mastering and I/O,memory access 278 */ 279 ixp425_pci_conf_reg_write(sc, PCI_COMMAND_STATUS_REG, 280 PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 281 PCI_COMMAND_MASTER_ENABLE); 282 283 /* 284 * Wait some more to ensure PCI devices have stabilised. 285 */ 286 DELAY(50000); 287 } 288
Indexes created Sat Sep 20 22:09:52 GMT 2025