nslu2_start.S revision 1.1.2.2
1 1.1.2.2 yamt /* $NetBSD: nslu2_start.S,v 1.1.2.2 2006/03/01 09:27:46 yamt Exp $ */ 2 1.1.2.2 yamt 3 1.1.2.2 yamt /* 4 1.1.2.2 yamt * Copyright (c) 2006 The NetBSD Foundation, Inc. 5 1.1.2.2 yamt * All rights reserved. 6 1.1.2.2 yamt * 7 1.1.2.2 yamt * This code is derived from software contributed to The NetBSD Foundation 8 1.1.2.2 yamt * by Ichiro FUKUHARA, Jason R. Thorpe, and Steve C. Woodford. 9 1.1.2.2 yamt * 10 1.1.2.2 yamt * Redistribution and use in source and binary forms, with or without 11 1.1.2.2 yamt * modification, are permitted provided that the following conditions 12 1.1.2.2 yamt * are met: 13 1.1.2.2 yamt * 1. Redistributions of source code must retain the above copyright 14 1.1.2.2 yamt * notice, this list of conditions and the following disclaimer. 15 1.1.2.2 yamt * 2. Redistributions in binary form must reproduce the above copyright 16 1.1.2.2 yamt * notice, this list of conditions and the following disclaimer in the 17 1.1.2.2 yamt * documentation and/or other materials provided with the distribution. 18 1.1.2.2 yamt * 3. All advertising materials mentioning features or use of this software 19 1.1.2.2 yamt * must display the following acknowledgement: 20 1.1.2.2 yamt * This product includes software developed by the NetBSD 21 1.1.2.2 yamt * Foundation, Inc. and its contributors. 22 1.1.2.2 yamt * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.1.2.2 yamt * contributors may be used to endorse or promote products derived 24 1.1.2.2 yamt * from this software without specific prior written permission. 25 1.1.2.2 yamt * 26 1.1.2.2 yamt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.1.2.2 yamt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.1.2.2 yamt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.1.2.2 yamt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.1.2.2 yamt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.1.2.2 yamt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.1.2.2 yamt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.1.2.2 yamt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.1.2.2 yamt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.1.2.2 yamt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.1.2.2 yamt * POSSIBILITY OF SUCH DAMAGE. 37 1.1.2.2 yamt */ 38 1.1.2.2 yamt 39 1.1.2.2 yamt #include <machine/asm.h> 40 1.1.2.2 yamt #include <arm/armreg.h> 41 1.1.2.2 yamt #include <arm/arm32/pte.h> 42 1.1.2.2 yamt 43 1.1.2.2 yamt #include <arm/xscale/ixp425reg.h> 44 1.1.2.2 yamt 45 1.1.2.2 yamt .section .start,"ax",%progbits 46 1.1.2.2 yamt 47 1.1.2.2 yamt .global _C_LABEL(nslu2_start) 48 1.1.2.2 yamt _C_LABEL(nslu2_start): 49 1.1.2.2 yamt /* 50 1.1.2.2 yamt * We will go ahead and disable the MMU here so that we don't 51 1.1.2.2 yamt * have to worry about flushing caches, etc. 52 1.1.2.2 yamt * 53 1.1.2.2 yamt * Note that we may not currently be running VA==PA, which means 54 1.1.2.2 yamt * we'll need to leap to the next insn after disabing the MMU. 55 1.1.2.2 yamt */ 56 1.1.2.2 yamt adr r8, Lunmapped 57 1.1.2.2 yamt bic r8, r8, #0xff000000 /* clear upper 8 bits */ 58 1.1.2.2 yamt orr r8, r8, #0x10000000 /* OR in physical base address */ 59 1.1.2.2 yamt 60 1.1.2.2 yamt mrc p15, 0, r2, c1, c0, 0 61 1.1.2.2 yamt bic r2, r2, #CPU_CONTROL_MMU_ENABLE 62 1.1.2.2 yamt orr r2, r2, #CPU_CONTROL_BEND_ENABLE 63 1.1.2.2 yamt mcr p15, 0, r2, c1, c0, 0 64 1.1.2.2 yamt 65 1.1.2.2 yamt nop 66 1.1.2.2 yamt nop 67 1.1.2.2 yamt nop 68 1.1.2.2 yamt 69 1.1.2.2 yamt mov pc, r8 /* Heave-ho! */ 70 1.1.2.2 yamt 71 1.1.2.2 yamt Lunmapped: 72 1.1.2.2 yamt /* 73 1.1.2.2 yamt * We want to construct a memory map that maps us 74 1.1.2.2 yamt * VA==PA (SDRAM at 0x10000000). We create these 75 1.1.2.2 yamt * mappings uncached and unbuffered to be safe. 76 1.1.2.2 yamt */ 77 1.1.2.2 yamt 78 1.1.2.2 yamt /* 79 1.1.2.2 yamt * Step 1: Map the entire address space VA==PA. 80 1.1.2.2 yamt */ 81 1.1.2.2 yamt adr r0, Ltable 82 1.1.2.2 yamt ldr r0, [r0] /* r0 = &l1table */ 83 1.1.2.2 yamt 84 1.1.2.2 yamt mov r1, #(L1_TABLE_SIZE / 4) /* 4096 entry */ 85 1.1.2.2 yamt mov r2, #(L1_S_SIZE) /* 1MB / section */ 86 1.1.2.2 yamt mov r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */ 87 1.1.2.2 yamt orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 88 1.1.2.2 yamt 1: 89 1.1.2.2 yamt str r3, [r0], #0x04 90 1.1.2.2 yamt add r3, r3, r2 91 1.1.2.2 yamt subs r1, r1, #1 92 1.1.2.2 yamt bgt 1b 93 1.1.2.2 yamt 94 1.1.2.2 yamt /* 95 1.1.2.2 yamt * Step 2: Map VA 0xc0000000->0xc3ffffff to PA 0x10000000->0x13ffffff. 96 1.1.2.2 yamt */ 97 1.1.2.2 yamt adr r0, Ltable /* r0 = &l1table */ 98 1.1.2.2 yamt ldr r0, [r0] 99 1.1.2.2 yamt 100 1.1.2.2 yamt mov r3, #(L1_S_AP(AP_KRW)) 101 1.1.2.2 yamt orr r3, r3, #(L1_TYPE_S) 102 1.1.2.2 yamt orr r3, r3, #0x10000000 103 1.1.2.2 yamt add r0, r0, #(0xc00 * 4) /* offset to 0xc00xxxxx */ 104 1.1.2.2 yamt mov r1, #0x40 /* 64MB */ 105 1.1.2.2 yamt 1: 106 1.1.2.2 yamt str r3, [r0], #0x04 107 1.1.2.2 yamt add r3, r3, r2 108 1.1.2.2 yamt subs r1, r1, #1 109 1.1.2.2 yamt bgt 1b 110 1.1.2.2 yamt 111 1.1.2.2 yamt /* 112 1.1.2.2 yamt * Step 3: Map VA 0xf0000000->0xf0100000 to PA 0xc8000000->0xc8100000. 113 1.1.2.2 yamt */ 114 1.1.2.2 yamt adr r0, Ltable /* r0 = &l1table */ 115 1.1.2.2 yamt ldr r0, [r0] 116 1.1.2.2 yamt 117 1.1.2.2 yamt add r0, r0, #(0xf00 * 4) /* offset to 0xf0000000 */ 118 1.1.2.2 yamt mov r3, #0xc8000000 119 1.1.2.2 yamt add r3, r3, #0x00100000 120 1.1.2.2 yamt orr r3, r3, #(L1_S_AP(AP_KRW)) 121 1.1.2.2 yamt orr r3, r3, #(L1_TYPE_S) 122 1.1.2.2 yamt str r3, [r0] 123 1.1.2.2 yamt 124 1.1.2.2 yamt /* 125 1.1.2.2 yamt * Step 4: Map VA 0xf0200000->0xf0300000 to PA 0xcc000000->0xcc100000. 126 1.1.2.2 yamt */ 127 1.1.2.2 yamt adr r0, Ltable /* r0 = &l1table */ 128 1.1.2.2 yamt ldr r0, [r0] 129 1.1.2.2 yamt 130 1.1.2.2 yamt add r0, r0, #(0xf00 * 4) /* offset to 0xf0200000 */ 131 1.1.2.2 yamt add r0, r0, #(0x002 * 4) 132 1.1.2.2 yamt mov r3, #0xcc000000 133 1.1.2.2 yamt add r3, r3, #0x00100000 134 1.1.2.2 yamt orr r3, r3, #(L1_S_AP(AP_KRW)) 135 1.1.2.2 yamt orr r3, r3, #(L1_TYPE_S) 136 1.1.2.2 yamt str r3, [r0] 137 1.1.2.2 yamt 138 1.1.2.2 yamt /* OK! Page table is set up. Give it to the CPU. */ 139 1.1.2.2 yamt adr r0, Ltable 140 1.1.2.2 yamt ldr r0, [r0] 141 1.1.2.2 yamt mcr p15, 0, r0, c2, c0, 0 142 1.1.2.2 yamt 143 1.1.2.2 yamt /* Flush the old TLBs, just in case. */ 144 1.1.2.2 yamt mcr p15, 0, r0, c8, c7, 0 145 1.1.2.2 yamt 146 1.1.2.2 yamt /* Set the Domain Access register. Very important! */ 147 1.1.2.2 yamt mov r0, #1 148 1.1.2.2 yamt mcr p15, 0, r0, c3, c0, 0 149 1.1.2.2 yamt 150 1.1.2.2 yamt /* Get ready to jump to the "real" kernel entry point... */ 151 1.1.2.2 yamt ldr r1, Lstart 152 1.1.2.2 yamt mov r1, r1 /* Make sure the load completes! */ 153 1.1.2.2 yamt 154 1.1.2.2 yamt /* OK, let's enable the MMU. */ 155 1.1.2.2 yamt mrc p15, 0, r2, c1, c0, 0 156 1.1.2.2 yamt orr r2, r2, #CPU_CONTROL_MMU_ENABLE 157 1.1.2.2 yamt orr r2, r2, #CPU_CONTROL_BEND_ENABLE 158 1.1.2.2 yamt mcr p15, 0, r2, c1, c0, 0 159 1.1.2.2 yamt 160 1.1.2.2 yamt nop 161 1.1.2.2 yamt nop 162 1.1.2.2 yamt nop 163 1.1.2.2 yamt 164 1.1.2.2 yamt /* CPWAIT sequence to make sure the MMU is on... */ 165 1.1.2.2 yamt mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 166 1.1.2.2 yamt mov r2, r2 /* force it to complete */ 167 1.1.2.2 yamt mov pc, r1 /* leap to kernel entry point! */ 168 1.1.2.2 yamt 169 1.1.2.2 yamt Ltable: 170 1.1.2.2 yamt .word 0x10200000 - 0x4000 171 1.1.2.2 yamt 172 1.1.2.2 yamt Lstart: 173 1.1.2.2 yamt .word start 174
Indexes created Sun Oct 19 02:09:48 GMT 2025