tsarm_start.S revision 1.1
1 /* $NetBSD: tsarm_start.S,v 1.1 2004/12/23 04:28:31 joff Exp $ */ 2 3 /* 4 * Copyright (c) 2003 5 * Ichiro FUKUHARA <ichiro (at) ichiro.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Ichiro FUKUHARA. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 #include <machine/asm.h> 36 #include <arm/armreg.h> 37 #include <arm/arm32/pte.h> 38 39 #include <arm/ep93xx/ep93xxreg.h> 40 41 .section .start,"ax",%progbits 42 43 .global _C_LABEL(ts7xxx_start) 44 _C_LABEL(ts7xxx_start): 45 46 /* 47 * We will go ahead and disable the MMU here so that we don't 48 * have to worry about flushing caches, etc. 49 * 50 * Note that we may not currently be running VA==PA, which means 51 * we'll need to leap to the next insn after disabing the MMU. 52 */ 53 adr r8, Lunmapped 54 bic r8, r8, #0xff000000 /* clear upper 8 bits */ 55 56 /* 57 * Setup coprocessor 15. 58 */ 59 mrc p15, 0, r2, c1, c0, 0 60 bic r2, r2, #CPU_CONTROL_MMU_ENABLE 61 mcr p15, 0, r2, c1, c0, 0 62 63 nop 64 nop 65 nop 66 67 mov pc, r8 /* Heave-ho! */ 68 69 Lunmapped: 70 /* 71 * We want to construct a memory map that maps us 72 * VA==PA (SDRAM at 0x00000000). We create these 73 * mappings uncached and unbuffered to be safe. 74 */ 75 /* 76 * Step 1: Map the entire address space VA==PA. 77 */ 78 adr r4, Ltable 79 ldr r0, [r4] /* r0 = &l1table */ 80 81 mov r1, #(L1_TABLE_SIZE / 4) /* 4096 entry */ 82 mov r2, #(L1_S_SIZE) /* 1MB / section */ 83 mov r3, #(L1_S_AP(AP_KRW)) /* kernel read/write */ 84 orr r3, r3, #(L1_TYPE_S) /* L1 entry is section */ 85 1: 86 str r3, [r0], #0x04 87 add r3, r3, r2 88 subs r1, r1, #1 89 bgt 1b 90 91 92 /* 93 * Step 2: Map VA 0xc0000000->0xc07fffff to PA 0x00000000->0x007fffff. 94 */ 95 ldr r0, [r4] 96 add r0, r0, #(0xc00 * 4) /* offset to 0xc00xxxxx */ 97 98 mov r1, #0x8 /* 8MB */ 99 mov r3, #(L1_S_AP(AP_KRW)) 100 orr r3, r3, #(L1_TYPE_S) 101 1: 102 str r3, [r0], #0x04 103 add r3, r3, r2 104 subs r1, r1, #1 105 bgt 1b 106 107 /* 108 * Step 3: Map VA 0xf0000000->0xf0100000 to PA 0x80000000->0x80100000. 109 */ 110 ldr r0, [r4] 111 112 add r0, r0, #(0xf00 * 4) /* offset to 0xf0000000 */ 113 mov r3, #0x80000000 114 orr r3, r3, #(L1_S_AP(AP_KRW)) 115 orr r3, r3, #(L1_TYPE_S) 116 str r3, [r0], #4 117 118 /* 119 * Step 4: Map VA 0xf0100000->0xf0300000 to PA 0x80800000->0x80a00000. 120 */ 121 mov r3, #0x80000000 122 add r3, r3, #0x00800000 123 orr r3, r3, #(L1_S_AP(AP_KRW)) 124 orr r3, r3, #(L1_TYPE_S) 125 str r3, [r0], #0x4 126 add r3, r3, r2 127 str r3, [r0], #0x4 128 129 /* 130 * Step 5: Map VA 0xf0300000->0xf4300000 to PA 0x10000000->0x14000000. 131 */ 132 mov r1, #0x40 /* 64MB */ 133 mov r3, #(L1_S_AP(AP_KRW)) 134 orr r3, r3, #(L1_TYPE_S) 135 orr r3, r3, #0x10000000 136 1: 137 str r3, [r0], #0x04 138 add r3, r3, r2 139 subs r1, r1, #1 140 bgt 1b 141 142 /* 143 * Step 6: Map VA 0xf4300000->0xf8300000 to PA 0x20000000->0x24000000. 144 */ 145 mov r1, #0x40 /* 64MB */ 146 mov r3, #(L1_S_AP(AP_KRW)) 147 orr r3, r3, #(L1_TYPE_S) 148 orr r3, r3, #0x20000000 149 1: 150 str r3, [r0], #0x04 151 add r3, r3, r2 152 subs r1, r1, #1 153 bgt 1b 154 155 156 /* OK! Page table is set up. Give it to the CPU. */ 157 adr r0, Ltable 158 ldr r0, [r0] 159 mcr p15, 0, r0, c2, c0, 0 160 161 /* Flush the old TLBs, just in case. */ 162 mcr p15, 0, r0, c8, c7, 0 163 164 /* Set the Domain Access register. Very important! */ 165 mov r0, #1 166 mcr p15, 0, r0, c3, c0, 0 167 168 /* Get ready to jump to the "real" kernel entry point... */ 169 ldr r1, Lstart 170 mov r1, r1 /* Make sure the load completes! */ 171 172 /* OK, let's enable the MMU. */ 173 mrc p15, 0, r2, c1, c0, 0 174 orr r2, r2, #CPU_CONTROL_MMU_ENABLE 175 mcr p15, 0, r2, c1, c0, 0 176 177 nop 178 nop 179 nop 180 181 /* CPWAIT sequence to make sure the MMU is on... */ 182 mrc p15, 0, r2, c2, c0, 0 /* arbitrary read of CP15 */ 183 mov r2, r2 /* force it to complete */ 184 mov pc, r1 /* leap to kernel entry point! */ 185 186 Ltable: 187 .word 0x4000 188 189 Lstart: 190 .word start 191
Indexes created Mon Sep 29 21:09:56 GMT 2025