1 1.14 matt /* $NetBSD: mcclock_isa.c,v 1.14 2011/07/08 18:49:48 matt Exp $ */ 2 1.1 simonb 3 1.1 simonb /* 4 1.1 simonb * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 1.1 simonb * All rights reserved. 6 1.1 simonb * 7 1.1 simonb * Author: Chris G. Demetriou 8 1.1 simonb * 9 1.1 simonb * Permission to use, copy, modify and distribute this software and 10 1.1 simonb * its documentation is hereby granted, provided that both the copyright 11 1.1 simonb * notice and this permission notice appear in all copies of the 12 1.1 simonb * software, derivative works or modified versions, and any portions 13 1.1 simonb * thereof, and that both notices appear in supporting documentation. 14 1.1 simonb * 15 1.1 simonb * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 1.1 simonb * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 1.1 simonb * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 1.1 simonb * 19 1.1 simonb * Carnegie Mellon requests users of this software to return to 20 1.1 simonb * 21 1.1 simonb * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 1.1 simonb * School of Computer Science 23 1.1 simonb * Carnegie Mellon University 24 1.1 simonb * Pittsburgh PA 15213-3890 25 1.1 simonb * 26 1.1 simonb * any improvements or extensions that they make and grant Carnegie the 27 1.1 simonb * rights to redistribute these changes. 28 1.1 simonb */ 29 1.1 simonb 30 1.1 simonb #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 31 1.1 simonb 32 1.14 matt __KERNEL_RCSID(0, "$NetBSD: mcclock_isa.c,v 1.14 2011/07/08 18:49:48 matt Exp $"); 33 1.1 simonb 34 1.1 simonb #include <sys/param.h> 35 1.1 simonb #include <sys/kernel.h> 36 1.1 simonb #include <sys/systm.h> 37 1.1 simonb #include <sys/device.h> 38 1.1 simonb 39 1.13 dyoung #include <sys/bus.h> 40 1.1 simonb 41 1.7 gdamore #include <dev/clock_subr.h> 42 1.1 simonb #include <dev/ic/mc146818reg.h> 43 1.7 gdamore #include <dev/ic/mc146818var.h> 44 1.1 simonb 45 1.2 simonb #include <dev/isa/isareg.h> 46 1.1 simonb #include <dev/isa/isavar.h> 47 1.1 simonb 48 1.7 gdamore /* 49 1.7 gdamore * Note the Algorithmics PMON firmware uses a different year base. 50 1.7 gdamore */ 51 1.7 gdamore #define ALGOR_YEAR_ZERO 1920 52 1.1 simonb 53 1.11 tsutsui static int mcclock_isa_match(device_t, cfdata_t, void *); 54 1.14 matt static void mcclock_isa_attach(device_t, device_t, void *); 55 1.1 simonb 56 1.14 matt CFATTACH_DECL_NEW(mcclock_isa, sizeof(struct mc146818_softc), 57 1.4 thorpej mcclock_isa_match, mcclock_isa_attach, NULL, NULL); 58 1.1 simonb 59 1.7 gdamore static void mcclock_isa_write(struct mc146818_softc *, u_int, u_int); 60 1.7 gdamore static u_int mcclock_isa_read(struct mc146818_softc *, u_int); 61 1.1 simonb 62 1.1 simonb static int 63 1.11 tsutsui mcclock_isa_match(device_t parent, cfdata_t cf, void *aux) 64 1.1 simonb { 65 1.1 simonb struct isa_attach_args *ia = aux; 66 1.1 simonb bus_space_handle_t ioh; 67 1.1 simonb 68 1.1 simonb if (ia->ia_nio < 1 || 69 1.5 drochner (ia->ia_io[0].ir_addr != ISA_UNKNOWN_PORT && 70 1.2 simonb ia->ia_io[0].ir_addr != IO_RTC)) 71 1.1 simonb return (0); 72 1.1 simonb 73 1.1 simonb if (ia->ia_niomem > 0 && 74 1.5 drochner (ia->ia_iomem[0].ir_addr != ISA_UNKNOWN_IOMEM)) 75 1.1 simonb return (0); 76 1.1 simonb 77 1.1 simonb if (ia->ia_nirq > 0 && 78 1.5 drochner (ia->ia_irq[0].ir_irq != ISA_UNKNOWN_IRQ)) 79 1.1 simonb return (0); 80 1.1 simonb 81 1.1 simonb if (ia->ia_ndrq > 0 && 82 1.5 drochner (ia->ia_drq[0].ir_drq != ISA_UNKNOWN_DRQ)) 83 1.1 simonb return (0); 84 1.1 simonb 85 1.2 simonb if (bus_space_map(ia->ia_iot, IO_RTC, 0x2, 0, &ioh)) 86 1.1 simonb return (0); 87 1.1 simonb 88 1.1 simonb bus_space_unmap(ia->ia_iot, ioh, 0x2); 89 1.1 simonb 90 1.1 simonb ia->ia_nio = 1; 91 1.2 simonb ia->ia_io[0].ir_addr = IO_RTC; 92 1.1 simonb ia->ia_io[0].ir_size = 0x02; 93 1.1 simonb 94 1.1 simonb ia->ia_niomem = 0; 95 1.1 simonb ia->ia_nirq = 0; 96 1.1 simonb ia->ia_ndrq = 0; 97 1.1 simonb 98 1.1 simonb return (1); 99 1.1 simonb } 100 1.1 simonb 101 1.1 simonb static void 102 1.11 tsutsui mcclock_isa_attach(device_t parent, device_t self, void *aux) 103 1.1 simonb { 104 1.11 tsutsui struct mc146818_softc *sc = device_private(self); 105 1.1 simonb struct isa_attach_args *ia = aux; 106 1.1 simonb 107 1.12 tsutsui sc->sc_dev = self; 108 1.7 gdamore sc->sc_bst = ia->ia_iot; 109 1.7 gdamore if (bus_space_map(sc->sc_bst, ia->ia_io[0].ir_addr, 110 1.7 gdamore ia->ia_io[0].ir_size, 0, &sc->sc_bsh)) 111 1.1 simonb panic("mcclock_isa_attach: couldn't map clock I/O space"); 112 1.1 simonb 113 1.7 gdamore sc->sc_year0 = ALGOR_YEAR_ZERO; 114 1.7 gdamore sc->sc_flag = MC146818_NO_CENT_ADJUST; 115 1.7 gdamore sc->sc_mcread = mcclock_isa_read; 116 1.7 gdamore sc->sc_mcwrite = mcclock_isa_write; 117 1.7 gdamore sc->sc_getcent = NULL; 118 1.7 gdamore sc->sc_setcent = NULL; 119 1.7 gdamore 120 1.7 gdamore /* 121 1.7 gdamore * Turn interrupts off, just in case. Need to leave the SQWE 122 1.7 gdamore * set, because that's the DRAM refresh signal on Rev. B boards. 123 1.7 gdamore */ 124 1.7 gdamore mcclock_isa_write(sc, MC_REGB, MC_REGB_SQWE | MC_REGB_BINARY | 125 1.7 gdamore MC_REGB_24HR); 126 1.7 gdamore 127 1.7 gdamore mc146818_attach(sc); 128 1.14 matt 129 1.9 simonb aprint_normal("\n"); 130 1.1 simonb } 131 1.1 simonb 132 1.14 matt static void 133 1.7 gdamore mcclock_isa_write(struct mc146818_softc *sc, u_int reg, u_int datum) 134 1.1 simonb { 135 1.7 gdamore bus_space_tag_t iot = sc->sc_bst; 136 1.7 gdamore bus_space_handle_t ioh = sc->sc_bsh; 137 1.1 simonb 138 1.1 simonb bus_space_write_1(iot, ioh, 0, reg); 139 1.1 simonb bus_space_write_1(iot, ioh, 1, datum); 140 1.1 simonb } 141 1.1 simonb 142 1.14 matt static u_int 143 1.7 gdamore mcclock_isa_read(struct mc146818_softc *sc, u_int reg) 144 1.1 simonb { 145 1.7 gdamore bus_space_tag_t iot = sc->sc_bst; 146 1.7 gdamore bus_space_handle_t ioh = sc->sc_bsh; 147 1.1 simonb 148 1.1 simonb bus_space_write_1(iot, ioh, 0, reg); 149 1.1 simonb return bus_space_read_1(iot, ioh, 1); 150 1.1 simonb } 151