1 /* $NetBSD: gt.c,v 1.17 2021/08/07 16:18:51 thorpej Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.17 2021/08/07 16:18:51 thorpej Exp $"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <dev/pci/pcivar.h> 46 47 #include <mips/cpuregs.h> 48 49 #include <evbmips/malta/maltareg.h> 50 #include <evbmips/malta/maltavar.h> 51 52 #include <evbmips/malta/dev/gtreg.h> 53 #include <evbmips/malta/dev/gtvar.h> 54 55 #include "pci.h" 56 57 /* 58 * Galileo systems (so far) are always single-processor, so this is sufficient. 59 */ 60 #define PCI_CONF_LOCK(s) (s) = splhigh() 61 #define PCI_CONF_UNLOCK(s) splx((s)) 62 63 static void gt_attach_hook(device_t, device_t, struct pcibus_attach_args *); 64 static int gt_bus_maxdevs(void *, int); 65 static pcitag_t gt_make_tag(void *, int, int, int); 66 static void gt_decompose_tag(void *, pcitag_t, int *, int *, int *); 67 static pcireg_t gt_conf_read(void *, pcitag_t, int); 68 static void gt_conf_write(void *, pcitag_t, int, pcireg_t); 69 70 void 71 gt_pci_init(pci_chipset_tag_t pc, struct gt_config *mcp) 72 { 73 74 pc->pc_conf_v = mcp; 75 pc->pc_attach_hook = gt_attach_hook; 76 pc->pc_bus_maxdevs = gt_bus_maxdevs; 77 pc->pc_make_tag = gt_make_tag; 78 pc->pc_decompose_tag = gt_decompose_tag; 79 pc->pc_conf_read = gt_conf_read; 80 pc->pc_conf_write = gt_conf_write; 81 } 82 83 static void 84 gt_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 85 { 86 87 /* Nothing to do... */ 88 } 89 90 static int gt_match(device_t, cfdata_t, void *); 91 static void gt_attach(device_t, device_t, void *); 92 static int gt_print(void *aux, const char *pnp); 93 94 CFATTACH_DECL_NEW(gt, 0, 95 gt_match, gt_attach, NULL, NULL); 96 97 static int 98 gt_match(device_t parent, cfdata_t match, void *aux) 99 { 100 return 1; 101 } 102 103 static void 104 gt_attach(device_t parent, device_t self, void *aux) 105 { 106 struct malta_config *mcp = &malta_configuration; 107 struct pcibus_attach_args pba; 108 109 printf("\n"); 110 111 #if NPCI > 0 112 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 113 pba.pba_bus = 0; 114 pba.pba_bridgetag = NULL; 115 pba.pba_iot = &mcp->mc_iot; 116 pba.pba_memt = &mcp->mc_memt; 117 pba.pba_dmat = &mcp->mc_pci_dmat; /* pci_bus_dma_tag */ 118 pba.pba_dmat64 = NULL; 119 pba.pba_pc = &mcp->mc_pc; 120 121 config_found(self, &pba, gt_print, CFARGS_NONE); 122 #endif 123 } 124 125 static int 126 gt_print(void *aux, const char *pnp) 127 { 128 /* XXX */ 129 return 0; 130 } 131 132 static int 133 gt_bus_maxdevs(void *v, int busno) 134 { 135 136 /* The galileo has problems accessing device 31. */ 137 if (busno == 0) 138 return (31); 139 return (32); 140 } 141 142 static pcitag_t 143 gt_make_tag(void *v, int b, int d, int f) 144 { 145 146 return ((b << 16) | (d << 11) | (f << 8)); 147 } 148 149 static void 150 gt_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 151 { 152 153 if (bp != NULL) 154 *bp = (tag >> 16) & 0xff; 155 if (dp != NULL) 156 *dp = (tag >> 11) & 0x1f; 157 if (fp != NULL) 158 *fp = (tag >> 8) & 0x7; 159 } 160 161 static pcireg_t 162 gt_conf_read(void *v, pcitag_t tag, int offset) 163 { 164 pcireg_t data; 165 int bus, dev, func, s; 166 167 if ((unsigned int)offset >= PCI_CONF_SIZE) 168 return ((pcireg_t) -1); 169 170 gt_decompose_tag(NULL /* XXX */, tag, &bus, &dev, &func); 171 172 /* The galileo has problems accessing device 31. */ 173 if (bus == 0 && dev == 31) 174 return ((pcireg_t) -1); 175 176 /* XXX: no support for bus > 0 yet */ 177 if (bus > 0) 178 return ((pcireg_t) -1); 179 180 PCI_CONF_LOCK(s); 181 182 /* Clear cause register bits. */ 183 GT_REGVAL(GT_INTR_CAUSE) = 0; 184 185 GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset; 186 data = GT_REGVAL(GT_PCI0_CFG_DATA); 187 188 /* Check for master abort. */ 189 if (GT_REGVAL(GT_INTR_CAUSE) & (GTIC_MASABORT0 | GTIC_TARABORT0)) 190 data = (pcireg_t) -1; 191 192 PCI_CONF_UNLOCK(s); 193 194 return (data); 195 } 196 197 static void 198 gt_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data) 199 { 200 int bus, dev, func, s; 201 202 if ((unsigned int)offset >= PCI_CONF_SIZE) 203 return; 204 205 gt_decompose_tag(NULL /* XXX */, tag, &bus, &dev, &func); 206 207 /* The galileo has problems accessing device 31. */ 208 if (bus == 0 && dev == 31) 209 return; 210 211 /* XXX: no support for bus > 0 yet */ 212 if (bus > 0) 213 return; 214 215 PCI_CONF_LOCK(s); 216 217 /* Clear cause register bits. */ 218 GT_REGVAL(GT_INTR_CAUSE) = 0; 219 220 GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset; 221 GT_REGVAL(GT_PCI0_CFG_DATA) = data; 222 223 PCI_CONF_UNLOCK(s); 224 } 225
Indexes created Sat Sep 20 22:09:52 GMT 2025