gt.c revision 1.2 1 /* $NetBSD: gt.c,v 1.2 2002/05/16 01:01:36 thorpej Exp $ */
2
3 /*
4 * Copyright 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/device.h>
41
42 #include <dev/pci/pcivar.h>
43
44 #include <evbmips/malta/maltareg.h>
45 #include <evbmips/malta/maltavar.h>
46
47 #include <evbmips/malta/dev/gtreg.h>
48 #include <evbmips/malta/dev/gtvar.h>
49
50 #include "pci.h"
51
52 /*
53 * Galileo systems (so far) are always single-processor, so this is sufficient.
54 */
55 #define PCI_CONF_LOCK(s) (s) = splhigh()
56 #define PCI_CONF_UNLOCK(s) splx((s))
57
58 static void gt_attach_hook(struct device *, struct device *,
59 struct pcibus_attach_args *);
60 static int gt_bus_maxdevs(void *, int);
61 static pcitag_t gt_make_tag(void *, int, int, int);
62 static void gt_decompose_tag(void *, pcitag_t, int *, int *, int *);
63 static pcireg_t gt_conf_read(void *, pcitag_t, int);
64 static void gt_conf_write(void *, pcitag_t, int, pcireg_t);
65
66 void
67 gt_pci_init(pci_chipset_tag_t pc, struct gt_config *mcp)
68 {
69
70 pc->pc_conf_v = mcp;
71 pc->pc_attach_hook = gt_attach_hook;
72 pc->pc_bus_maxdevs = gt_bus_maxdevs;
73 pc->pc_make_tag = gt_make_tag;
74 pc->pc_decompose_tag = gt_decompose_tag;
75 pc->pc_conf_read = gt_conf_read;
76 pc->pc_conf_write = gt_conf_write;
77 }
78
79 static void
80 gt_attach_hook(struct device *parent, struct device *self,
81 struct pcibus_attach_args *pba)
82 {
83
84 /* Nothing to do... */
85 }
86
87 static int gt_match(struct device *, struct cfdata *, void *);
88 static void gt_attach(struct device *, struct device *, void *);
89 static int gt_print(void *aux, const char *pnp);
90
91 struct cfattach gt_ca = {
92 sizeof(struct device), gt_match, gt_attach
93 };
94
95 static int
96 gt_match(parent, match, aux)
97 struct device *parent;
98 struct cfdata *match;
99 void *aux;
100 {
101 return 1;
102 }
103
104 static void
105 gt_attach(parent, self, aux)
106 struct device *parent;
107 struct device *self;
108 void *aux;
109 {
110 struct malta_config *mcp = &malta_configuration;
111 struct pcibus_attach_args pba;
112
113 printf("\n");
114
115 #if NPCI > 0
116 pba.pba_busname = "pci";
117 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
118 pba.pba_bus = 0;
119 pba.pba_bridgetag = NULL;
120 pba.pba_iot = &mcp->mc_iot;
121 pba.pba_memt = &mcp->mc_memt;
122 pba.pba_dmat = &mcp->mc_pci_dmat; /* pci_bus_dma_tag */
123 //pba.pba_dmat = &pci_bus_dma_tag;
124 pba.pba_pc = &mcp->mc_pc;
125
126 config_found(self, &pba, gt_print);
127 #endif
128 return;
129 }
130
131 static int
132 gt_print(aux, pnp)
133 void *aux;
134 const char *pnp;
135 {
136 /* XXX */
137 return 0;
138 }
139
140 static int
141 gt_bus_maxdevs(void *v, int busno)
142 {
143
144 /* The galileo has problems accessing device 31. */
145 if (busno == 0)
146 return (31);
147 return (32);
148 }
149
150 static pcitag_t
151 gt_make_tag(void *v, int b, int d, int f)
152 {
153
154 return ((b << 16) | (d << 11) | (f << 8));
155 }
156
157 static void
158 gt_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
159 {
160
161 if (bp != NULL)
162 *bp = (tag >> 16) & 0xff;
163 if (dp != NULL)
164 *dp = (tag >> 11) & 0x1f;
165 if (fp != NULL)
166 *fp = (tag >> 8) & 0x7;
167 }
168
169 static pcireg_t
170 gt_conf_read(void *v, pcitag_t tag, int offset)
171 {
172 pcireg_t data;
173 int bus, dev, func, s;
174
175 gt_decompose_tag(NULL /* XXX */, tag, &bus, &dev, &func);
176
177 /* The galileo has problems accessing device 31. */
178 if (bus == 0 && dev == 31)
179 return ((pcireg_t) -1);
180
181 /* XXX: no support for bus > 0 yet */
182 if (bus > 0)
183 return ((pcireg_t) -1);
184
185 PCI_CONF_LOCK(s);
186
187 /* Clear cause register bits. */
188 GT_REGVAL(GT_INTR_CAUSE) = 0;
189
190 GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset;
191 data = GT_REGVAL(GT_PCI0_CFG_DATA);
192
193 /* Check for master abort. */
194 if (GT_REGVAL(GT_INTR_CAUSE) & (GTIC_MASABORT0 | GTIC_TARABORT0))
195 data = (pcireg_t) -1;
196
197 PCI_CONF_UNLOCK(s);
198
199 return (data);
200 }
201
202 static void
203 gt_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data)
204 {
205 int bus, dev, func, s;
206
207 gt_decompose_tag(NULL /* XXX */, tag, &bus, &dev, &func);
208
209 /* The galileo has problems accessing device 31. */
210 if (bus == 0 && dev == 31)
211 return;
212
213 /* XXX: no support for bus > 0 yet */
214 if (bus > 0)
215 return;
216
217 PCI_CONF_LOCK(s);
218
219 /* Clear cause register bits. */
220 GT_REGVAL(GT_INTR_CAUSE) = 0;
221
222 GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset;
223 GT_REGVAL(GT_PCI0_CFG_DATA) = data;
224
225 PCI_CONF_UNLOCK(s);
226 }
227