gt.c revision 1.5 1 /* $NetBSD: gt.c,v 1.5 2002/10/02 15:45:17 thorpej Exp $ */
2
3 /*
4 * Copyright 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/device.h>
41
42 #include <dev/pci/pcivar.h>
43
44 #include <evbmips/malta/maltareg.h>
45 #include <evbmips/malta/maltavar.h>
46
47 #include <evbmips/malta/dev/gtreg.h>
48 #include <evbmips/malta/dev/gtvar.h>
49
50 #include "pci.h"
51
52 /*
53 * Galileo systems (so far) are always single-processor, so this is sufficient.
54 */
55 #define PCI_CONF_LOCK(s) (s) = splhigh()
56 #define PCI_CONF_UNLOCK(s) splx((s))
57
58 static void gt_attach_hook(struct device *, struct device *,
59 struct pcibus_attach_args *);
60 static int gt_bus_maxdevs(void *, int);
61 static pcitag_t gt_make_tag(void *, int, int, int);
62 static void gt_decompose_tag(void *, pcitag_t, int *, int *, int *);
63 static pcireg_t gt_conf_read(void *, pcitag_t, int);
64 static void gt_conf_write(void *, pcitag_t, int, pcireg_t);
65
66 void
67 gt_pci_init(pci_chipset_tag_t pc, struct gt_config *mcp)
68 {
69
70 pc->pc_conf_v = mcp;
71 pc->pc_attach_hook = gt_attach_hook;
72 pc->pc_bus_maxdevs = gt_bus_maxdevs;
73 pc->pc_make_tag = gt_make_tag;
74 pc->pc_decompose_tag = gt_decompose_tag;
75 pc->pc_conf_read = gt_conf_read;
76 pc->pc_conf_write = gt_conf_write;
77 }
78
79 static void
80 gt_attach_hook(struct device *parent, struct device *self,
81 struct pcibus_attach_args *pba)
82 {
83
84 /* Nothing to do... */
85 }
86
87 static int gt_match(struct device *, struct cfdata *, void *);
88 static void gt_attach(struct device *, struct device *, void *);
89 static int gt_print(void *aux, const char *pnp);
90
91 CFATTACH_DECL(gt, sizeof(struct device),
92 gt_match, gt_attach, NULL, NULL);
93
94 static int
95 gt_match(parent, match, aux)
96 struct device *parent;
97 struct cfdata *match;
98 void *aux;
99 {
100 return 1;
101 }
102
103 static void
104 gt_attach(parent, self, aux)
105 struct device *parent;
106 struct device *self;
107 void *aux;
108 {
109 struct malta_config *mcp = &malta_configuration;
110 struct pcibus_attach_args pba;
111
112 printf("\n");
113
114 #if NPCI > 0
115 pba.pba_busname = "pci";
116 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
117 pba.pba_bus = 0;
118 pba.pba_bridgetag = NULL;
119 pba.pba_iot = &mcp->mc_iot;
120 pba.pba_memt = &mcp->mc_memt;
121 pba.pba_dmat = &mcp->mc_pci_dmat; /* pci_bus_dma_tag */
122 //pba.pba_dmat = &pci_bus_dma_tag;
123 pba.pba_pc = &mcp->mc_pc;
124
125 config_found(self, &pba, gt_print);
126 #endif
127 return;
128 }
129
130 static int
131 gt_print(aux, pnp)
132 void *aux;
133 const char *pnp;
134 {
135 /* XXX */
136 return 0;
137 }
138
139 static int
140 gt_bus_maxdevs(void *v, int busno)
141 {
142
143 /* The galileo has problems accessing device 31. */
144 if (busno == 0)
145 return (31);
146 return (32);
147 }
148
149 static pcitag_t
150 gt_make_tag(void *v, int b, int d, int f)
151 {
152
153 return ((b << 16) | (d << 11) | (f << 8));
154 }
155
156 static void
157 gt_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
158 {
159
160 if (bp != NULL)
161 *bp = (tag >> 16) & 0xff;
162 if (dp != NULL)
163 *dp = (tag >> 11) & 0x1f;
164 if (fp != NULL)
165 *fp = (tag >> 8) & 0x7;
166 }
167
168 static pcireg_t
169 gt_conf_read(void *v, pcitag_t tag, int offset)
170 {
171 pcireg_t data;
172 int bus, dev, func, s;
173
174 gt_decompose_tag(NULL /* XXX */, tag, &bus, &dev, &func);
175
176 /* The galileo has problems accessing device 31. */
177 if (bus == 0 && dev == 31)
178 return ((pcireg_t) -1);
179
180 /* XXX: no support for bus > 0 yet */
181 if (bus > 0)
182 return ((pcireg_t) -1);
183
184 PCI_CONF_LOCK(s);
185
186 /* Clear cause register bits. */
187 GT_REGVAL(GT_INTR_CAUSE) = 0;
188
189 GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset;
190 data = GT_REGVAL(GT_PCI0_CFG_DATA);
191
192 /* Check for master abort. */
193 if (GT_REGVAL(GT_INTR_CAUSE) & (GTIC_MASABORT0 | GTIC_TARABORT0))
194 data = (pcireg_t) -1;
195
196 PCI_CONF_UNLOCK(s);
197
198 return (data);
199 }
200
201 static void
202 gt_conf_write(void *v, pcitag_t tag, int offset, pcireg_t data)
203 {
204 int bus, dev, func, s;
205
206 gt_decompose_tag(NULL /* XXX */, tag, &bus, &dev, &func);
207
208 /* The galileo has problems accessing device 31. */
209 if (bus == 0 && dev == 31)
210 return;
211
212 /* XXX: no support for bus > 0 yet */
213 if (bus > 0)
214 return;
215
216 PCI_CONF_LOCK(s);
217
218 /* Clear cause register bits. */
219 GT_REGVAL(GT_INTR_CAUSE) = 0;
220
221 GT_REGVAL(GT_PCI0_CFG_ADDR) = (1 << 31) | tag | offset;
222 GT_REGVAL(GT_PCI0_CFG_DATA) = data;
223
224 PCI_CONF_UNLOCK(s);
225 }
226