if_cs_mainbus.c revision 1.3
1 /* $NetBSD: if_cs_mainbus.c,v 1.3 2008/04/28 20:23:17 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at Sandburst Corp. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_cs_mainbus.c,v 1.3 2008/04/28 20:23:17 martin Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/systm.h> 38 #include <sys/socket.h> 39 40 #include "rnd.h" 41 #if NRND > 0 42 #include <sys/rnd.h> 43 #endif 44 45 #include <net/if.h> 46 #include <net/if_ether.h> 47 #include <net/if_media.h> 48 #ifdef INET 49 #include <netinet/in.h> 50 #include <netinet/if_inarp.h> 51 #endif 52 53 #include <machine/bus.h> 54 #include <machine/pio.h> 55 #include <machine/pmppc.h> 56 #include <arch/evbppc/pmppc/dev/mainbus.h> 57 58 #include <dev/ic/cs89x0reg.h> 59 #include <dev/ic/cs89x0var.h> 60 61 #include <sys/callout.h> 62 63 #define ATSN_EEPROM_MAC_OFFSET 0x20 64 65 66 static void cs_check_eeprom(struct cs_softc *sc); 67 68 static int cs_mainbus_match(struct device *, struct cfdata *, void *); 69 static void cs_mainbus_attach(struct device *, struct device *, void *); 70 71 CFATTACH_DECL(cs_mainbus, sizeof(struct cs_softc), 72 cs_mainbus_match, cs_mainbus_attach, NULL, NULL); 73 74 int 75 cs_mainbus_match(struct device *parent, struct cfdata *cf, void *aux) 76 { 77 struct mainbus_attach_args *maa = aux; 78 79 return (strcmp(maa->mb_name, "cs") == 0); 80 } 81 82 #if 0 83 static u_int64_t 84 in64(uint a) 85 { 86 union { 87 double d; 88 u_int64_t i; 89 } u; 90 double save, *dp = (double *)a; 91 u_int32_t msr, nmsr; 92 93 __asm volatile("mfmsr %0" : "=r"(msr)); 94 nmsr = (msr | PSL_FP) & ~(PSL_FE0 | PSL_FE1); 95 __asm volatile("mtmsr %0" :: "r"(nmsr)); 96 __asm volatile("mfmsr %0" : "=r"(nmsr)); /* some interlock nonsense */ 97 __asm volatile( 98 "stfd 0,%0\n\ 99 lfd 0,%1\n\ 100 stfd 0,%2\n\ 101 lfd 0,%0" 102 : "=m"(save), "=m"(*dp) 103 : "m"(u.d) 104 ); 105 __asm volatile ("eieio; sync"); 106 __asm volatile("mtmsr %0" :: "r"(msr)); 107 return (u.i); 108 } 109 #endif 110 111 static void 112 out64(uint a, u_int64_t v) 113 { 114 union { 115 double d; 116 u_int64_t i; 117 } u; 118 double save, *dp = (double *)a; 119 u_int32_t msr, nmsr; 120 int s; 121 122 s = splhigh(); 123 u.i = v; 124 __asm volatile("mfmsr %0" : "=r"(msr)); 125 nmsr = (msr | PSL_FP) & ~(PSL_FE0 | PSL_FE1); 126 __asm volatile("mtmsr %0" :: "r"(nmsr)); 127 __asm volatile("mfmsr %0" : "=r"(nmsr)); /* some interlock nonsense */ 128 __asm volatile( 129 "stfd 0,%0\n\ 130 lfd 0,%2\n\ 131 stfd 0,%1\n\ 132 lfd 0,%0" 133 : "=m"(save), "=m"(*dp) 134 : "m"(u.d) 135 ); 136 __asm volatile ("eieio; sync"); 137 __asm volatile("mtmsr %0" :: "r"(msr)); 138 splx(s); 139 } 140 141 static u_int8_t 142 cs_io_read_1(struct cs_softc *sc, bus_size_t offs) 143 { 144 u_int32_t a, v; 145 146 a = sc->sc_ioh + (offs << 2); 147 v = in8(a); 148 return v; 149 } 150 151 static u_int16_t 152 cs_io_read_2(struct cs_softc *sc, bus_size_t offs) 153 { 154 u_int32_t a, v; 155 156 a = sc->sc_ioh + (offs << 2); 157 v = in16(a); 158 return v; 159 } 160 161 static void 162 cs_io_read_multi_2(struct cs_softc *sc, bus_size_t offs, u_int16_t *buf, 163 bus_size_t cnt) 164 { 165 u_int32_t a, v; 166 167 a = sc->sc_ioh + (offs << 2); 168 while (cnt--) { 169 v = in16(a); 170 *buf++ = bswap16(v); 171 } 172 } 173 174 static void 175 cs_io_write_2(struct cs_softc *sc, bus_size_t offs, u_int16_t data) 176 { 177 u_int32_t a; 178 u_int64_t v; 179 180 a = sc->sc_ioh + (offs << 2); 181 v = (u_int64_t)data << 48; 182 out64(a, v); 183 184 (void)in16(a); /* CPC700 write post bug */ 185 } 186 187 static void 188 cs_io_write_multi_2(struct cs_softc *sc, bus_size_t offs, 189 const u_int16_t *buf, bus_size_t cnt) 190 { 191 u_int16_t v; 192 double save, *dp; 193 union { 194 double d; 195 u_int64_t i; 196 } u; 197 u_int32_t msr, nmsr; 198 int s; 199 200 dp = (double *)(sc->sc_ioh + (offs << 2)); 201 202 s = splhigh(); 203 __asm volatile("mfmsr %0" : "=r"(msr)); 204 nmsr = (msr | PSL_FP) & ~(PSL_FE0 | PSL_FE1); 205 __asm volatile("mtmsr %0" :: "r"(nmsr)); 206 __asm volatile("mfmsr %0" : "=r"(nmsr)); /* some interlock nonsense */ 207 __asm volatile("stfd 0,%0" : "=m"(save)); 208 209 while (cnt--) { 210 v = *buf++; 211 v = bswap16(v); 212 u.i = (u_int64_t)v << 48; 213 __asm volatile("lfd 0,%1\nstfd 0,%0" : "=m"(*dp) : "m"(u.d) ); 214 __asm volatile ("eieio; sync"); 215 } 216 __asm volatile("lfd 0,%0" :: "m"(save)); 217 __asm volatile("mtmsr %0" :: "r"(msr)); 218 splx(s); 219 } 220 221 static u_int16_t 222 cs_mem_read_2(struct cs_softc *sc, bus_size_t offs) 223 { 224 panic("cs_mem_read_2"); 225 } 226 227 static void 228 cs_mem_write_2(struct cs_softc *sc, bus_size_t offs, u_int16_t data) 229 { 230 panic("cs_mem_write_2"); 231 } 232 233 static void 234 cs_mem_write_region_2(struct cs_softc *sc, bus_size_t offs, 235 const u_int16_t *buf, bus_size_t cnt) 236 { 237 panic("cs_mem_write_region_2"); 238 } 239 240 void 241 cs_mainbus_attach(struct device *parent, struct device *self, void *aux) 242 { 243 struct cs_softc *sc = (struct cs_softc *)self; 244 struct mainbus_attach_args *maa = aux; 245 int media[1] = { IFM_ETHER | IFM_10_T }; 246 247 printf("\n"); 248 249 sc->sc_iot = maa->mb_bt; 250 sc->sc_memt = maa->mb_bt; 251 sc->sc_irq = maa->mb_irq; 252 253 if (bus_space_map(sc->sc_iot, PMPPC_CS_IO, CS8900_IOSIZE*4, 254 0, &sc->sc_ioh)) { 255 printf("%s: failed to map io\n", self->dv_xname); 256 return; 257 } 258 259 cs_check_eeprom(sc); 260 261 sc->sc_ih = intr_establish(sc->sc_irq, IST_LEVEL, IPL_NET, cs_intr, sc); 262 if (!sc->sc_ih) { 263 printf("%s: unable to establish interrupt\n", 264 self->dv_xname); 265 goto fail; 266 } 267 268 sc->sc_cfgflags = CFGFLG_NOT_EEPROM; 269 270 sc->sc_io_read_1 = cs_io_read_1; 271 sc->sc_io_read_2 = cs_io_read_2; 272 sc->sc_io_read_multi_2 = cs_io_read_multi_2; 273 sc->sc_io_write_2 = cs_io_write_2; 274 sc->sc_io_write_multi_2 = cs_io_write_multi_2; 275 sc->sc_mem_read_2 = cs_mem_read_2; 276 sc->sc_mem_write_2 = cs_mem_write_2; 277 sc->sc_mem_write_region_2 = cs_mem_write_region_2; 278 279 /* 280 * We need interrupt on INTRQ0 from the CS8900 (that's what wired 281 * to the UIC). The MI driver subtracts 10 from the irq, so 282 * use 10 as the irq. 283 */ 284 sc->sc_irq = 10; 285 286 /* Use half duplex 10baseT. */ 287 if (cs_attach(sc, NULL, media, 1, IFM_ETHER | IFM_10_T)) { 288 printf("%s: unable to attach\n", self->dv_xname); 289 goto fail; 290 } 291 292 return; 293 294 fail: 295 /* XXX disestablish, unmap */ 296 return; 297 } 298 299 300 /* 301 * EEPROM initialization code. 302 */ 303 304 static uint16_t default_eeprom_cfg[] = 305 { 0xA100, 0x2020, 0x0300, 0x0000, 0x0000, 306 0x102C, 0x1000, 0x0008, 0x2158, 0x0000, 307 0x0000, 0x0000 }; 308 309 static uint16_t 310 cs_readreg(struct cs_softc *sc, uint pp_offset) 311 { 312 cs_io_write_2(sc, PORT_PKTPG_PTR, pp_offset); 313 (void)cs_io_read_2(sc, PORT_PKTPG_PTR); 314 return (cs_io_read_2(sc, PORT_PKTPG_DATA)); 315 } 316 317 static void 318 cs_writereg(struct cs_softc *sc, uint pp_offset, uint16_t value) 319 { 320 cs_io_write_2(sc, PORT_PKTPG_PTR, pp_offset); 321 (void)cs_io_read_2(sc, PORT_PKTPG_PTR); 322 cs_io_write_2(sc, PORT_PKTPG_DATA, value); 323 (void)cs_io_read_2(sc, PORT_PKTPG_DATA); 324 } 325 326 static int 327 cs_wait_eeprom_ready(struct cs_softc *sc) 328 { 329 int ms; 330 331 /* 332 * Check to see if the EEPROM is ready, a timeout is used - 333 * just in case EEPROM is ready when SI_BUSY in the 334 * PP_SelfST is clear. 335 */ 336 ms = 0; 337 while(cs_readreg(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY) { 338 delay(1000); 339 if (ms++ > 20) 340 return 0; 341 } 342 return 1; 343 } 344 345 static void 346 cs_wr_eeprom(struct cs_softc *sc, uint16_t offset, uint16_t data) 347 { 348 349 /* Check to make sure EEPROM is ready. */ 350 if (!cs_wait_eeprom_ready(sc)) { 351 printf("%s: write EEPROM not ready\n", sc->sc_dev.dv_xname); 352 return; 353 } 354 355 /* Enable writing. */ 356 cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_WRITE_ENABLE); 357 358 /* Wait for WRITE_ENABLE command to complete. */ 359 if (!cs_wait_eeprom_ready(sc)) { 360 printf("%s: EEPROM WRITE_ENABLE timeout", sc->sc_dev.dv_xname); 361 } else { 362 /* Write data into EEPROM_DATA register. */ 363 cs_writereg(sc, PKTPG_EEPROM_DATA, data); 364 delay(1000); 365 cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_CMD_WRITE | offset); 366 367 /* Wait for WRITE_REGISTER command to complete. */ 368 if (!cs_wait_eeprom_ready(sc)) { 369 printf("%s: EEPROM WRITE_REGISTER timeout\n", 370 sc->sc_dev.dv_xname); 371 } 372 } 373 374 /* Disable writing. */ 375 cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_WRITE_DISABLE); 376 377 /* Wait for WRITE_DISABLE command to complete. */ 378 if (!cs_wait_eeprom_ready(sc)) { 379 printf("%s: WRITE_DISABLE timeout\n", sc->sc_dev.dv_xname); 380 } 381 } 382 383 static uint16_t 384 cs_rd_eeprom(struct cs_softc *sc, uint16_t offset) 385 { 386 387 if (!cs_wait_eeprom_ready(sc)) { 388 printf("%s: read EEPROM not ready\n", sc->sc_dev.dv_xname); 389 return 0; 390 } 391 cs_writereg(sc, PKTPG_EEPROM_CMD, EEPROM_CMD_READ | offset); 392 393 if (!cs_wait_eeprom_ready(sc)) { 394 printf("%s: EEPROM_READ timeout\n", sc->sc_dev.dv_xname); 395 return 0; 396 } 397 return cs_readreg(sc, PKTPG_EEPROM_DATA); 398 } 399 400 static void 401 cs_check_eeprom(struct cs_softc *sc) 402 { 403 uint8_t checksum; 404 int i; 405 uint16_t tmp; 406 407 /* 408 * If the SELFST[EEPROMOK] is set, then assume EEPROM configuration 409 * is valid. 410 */ 411 if (cs_readreg(sc, PKTPG_SELF_ST) & SELF_ST_EEP_OK) { 412 printf("%s: EEPROM OK, skipping initialization\n", 413 sc->sc_dev.dv_xname); 414 return; 415 } 416 printf("%s: updating EEPROM\n", sc->sc_dev.dv_xname); 417 418 /* 419 * Calculate the size (in bytes) of the default config array and write 420 * it to the lower byte of the array itself. 421 */ 422 default_eeprom_cfg[0] |= sizeof(default_eeprom_cfg); 423 424 /* 425 * Read the MAC address from its Artesyn-specified offset in the EEPROM. 426 */ 427 for (i = 0; i < 3; i++) { 428 tmp = cs_rd_eeprom(sc, ATSN_EEPROM_MAC_OFFSET + i); 429 default_eeprom_cfg[EEPROM_MAC + i] = bswap16(tmp); 430 } 431 432 /* 433 * Program the EEPROM with our default configuration, 434 * calculating checksum as we proceed. 435 */ 436 checksum = 0; 437 for (i = 0; i < sizeof(default_eeprom_cfg)/2 ; i++) { 438 tmp = default_eeprom_cfg[i]; 439 cs_wr_eeprom(sc, i, tmp); 440 checksum += tmp >> 8; 441 checksum += tmp & 0xff; 442 } 443 444 /* 445 * The CS8900a datasheet calls for the two's complement of the checksum 446 * to be prgrammed in the most significant byte of the last word of the 447 * header. 448 */ 449 checksum = ~checksum + 1; 450 cs_wr_eeprom(sc, i++, checksum << 8); 451 /* write "end of data" flag */ 452 cs_wr_eeprom(sc, i, 0xffff); 453 } 454
Indexes created Wed Oct 22 13:09:56 GMT 2025