11.1Sjmcneill/* $NetBSD: cache.h,v 1.1 2025/11/16 20:11:47 jmcneill Exp $ */ 21.1Sjmcneill 31.1Sjmcneill/*- 41.1Sjmcneill * Copyright (c) 2025 Jared McNeill <jmcneill@invisible.ca> 51.1Sjmcneill * All rights reserved. 61.1Sjmcneill * 71.1Sjmcneill * Redistribution and use in source and binary forms, with or without 81.1Sjmcneill * modification, are permitted provided that the following conditions 91.1Sjmcneill * are met: 101.1Sjmcneill * 1. Redistributions of source code must retain the above copyright 111.1Sjmcneill * notice, this list of conditions and the following disclaimer. 121.1Sjmcneill * 2. Redistributions in binary form must reproduce the above copyright 131.1Sjmcneill * notice, this list of conditions and the following disclaimer in the 141.1Sjmcneill * documentation and/or other materials provided with the distribution. 151.1Sjmcneill * 161.1Sjmcneill * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 171.1Sjmcneill * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 181.1Sjmcneill * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 191.1Sjmcneill * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 201.1Sjmcneill * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 211.1Sjmcneill * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 221.1Sjmcneill * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 231.1Sjmcneill * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 241.1Sjmcneill * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 251.1Sjmcneill * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 261.1Sjmcneill * SUCH DAMAGE. 271.1Sjmcneill */ 281.1Sjmcneill 291.1Sjmcneill#ifndef _WII_CACHE_H 301.1Sjmcneill#define _WII_CACHE_H 311.1Sjmcneill 321.1Sjmcneill#if CACHE_LINE_SIZE != 32 331.1Sjmcneill#error Incorrect CACHE_LINE_SIZE! 341.1Sjmcneill#endif 351.1Sjmcneill 361.1Sjmcneillstatic inline void 371.1Sjmcneillcache_dcbf(void *addr, size_t size) 381.1Sjmcneill{ 391.1Sjmcneill uint32_t start = ((uint32_t)addr & ~(CACHE_LINE_SIZE - 1)); 401.1Sjmcneill uint32_t end = roundup((uint32_t)addr + size, CACHE_LINE_SIZE); 411.1Sjmcneill 421.1Sjmcneill asm volatile("eieio"); 431.1Sjmcneill while (start < end) { 441.1Sjmcneill asm volatile("dcbf 0, %0" : : "r"(start) : "memory"); 451.1Sjmcneill start += CACHE_LINE_SIZE; 461.1Sjmcneill } 471.1Sjmcneill asm volatile("sync"); 481.1Sjmcneill} 491.1Sjmcneill 501.1Sjmcneillstatic inline void 511.1Sjmcneillcache_dcbi(void *addr, size_t size) 521.1Sjmcneill{ 531.1Sjmcneill uint32_t start = ((uint32_t)addr & ~(CACHE_LINE_SIZE - 1)); 541.1Sjmcneill uint32_t end = roundup((uint32_t)addr + size, CACHE_LINE_SIZE); 551.1Sjmcneill 561.1Sjmcneill asm volatile("eieio"); 571.1Sjmcneill while (start < end) { 581.1Sjmcneill asm volatile("dcbi 0, %0" : : "r"(start) : "memory"); 591.1Sjmcneill start += CACHE_LINE_SIZE; 601.1Sjmcneill } 611.1Sjmcneill asm volatile("sync"); 621.1Sjmcneill} 631.1Sjmcneill 641.1Sjmcneillstatic inline void 651.1Sjmcneillcache_icbi(void *addr, size_t size) 661.1Sjmcneill{ 671.1Sjmcneill uint32_t start = ((uint32_t)addr & ~(CACHE_LINE_SIZE - 1)); 681.1Sjmcneill uint32_t end = roundup((uint32_t)addr + size, CACHE_LINE_SIZE); 691.1Sjmcneill 701.1Sjmcneill asm volatile("eieio"); 711.1Sjmcneill while (start < end) { 721.1Sjmcneill asm volatile("icbi 0, %0" : : "r"(start) : "memory"); 731.1Sjmcneill start += CACHE_LINE_SIZE; 741.1Sjmcneill } 751.1Sjmcneill asm volatile("sync"); 761.1Sjmcneill} 771.1Sjmcneill 781.1Sjmcneill#endif /* !_WII_CACHE_H */ 79