1 /* $NetBSD: pic_pi.c,v 1.4 2025/03/13 18:41:34 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Processor interface interrupt controller. Top level controller for all 31 * EXT interrupts. 32 */ 33 34 #include <sys/cdefs.h> 35 36 __KERNEL_RCSID(0, "$NetBSD: pic_pi.c,v 1.4 2025/03/13 18:41:34 jmcneill Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/bitops.h> 43 #include <machine/pio.h> 44 #include <machine/intr.h> 45 #include <arch/powerpc/pic/picvar.h> 46 #include <machine/wii.h> 47 48 static uint32_t pic_irqmask; 49 static uint32_t pic_actmask; 50 51 void pi_init_intr(void); 52 53 #define WR4(reg, val) out32(reg, val) 54 #define RD4(reg) in32(reg) 55 56 static void 57 pi_enable_irq(struct pic_ops *pic, int irq, int type) 58 { 59 pic_irqmask |= __BIT(irq); 60 WR4(PI_INTMR, pic_irqmask & ~pic_actmask); 61 } 62 63 static void 64 pi_disable_irq(struct pic_ops *pic, int irq) 65 { 66 pic_irqmask &= ~__BIT(irq); 67 WR4(PI_INTMR, pic_irqmask & ~pic_actmask); 68 } 69 70 static int 71 pi_get_irq(struct pic_ops *pic, int mode) 72 { 73 uint32_t raw, pend; 74 int irq; 75 76 raw = RD4(PI_INTSR); 77 pend = raw & pic_irqmask; 78 if (pend == 0) { 79 return 255; 80 } 81 irq = ffs32(pend) - 1; 82 83 pic_actmask |= __BIT(irq); 84 WR4(PI_INTMR, pic_irqmask & ~pic_actmask); 85 86 return irq; 87 } 88 89 static void 90 pi_ack_irq(struct pic_ops *pic, int irq) 91 { 92 pic_actmask &= ~__BIT(irq); 93 WR4(PI_INTMR, pic_irqmask & ~pic_actmask); 94 WR4(PI_INTSR, __BIT(irq)); 95 } 96 97 static struct pic_ops pic = { 98 .pic_name = "pi", 99 .pic_numintrs = 32, 100 .pic_cookie = NULL, 101 .pic_enable_irq = pi_enable_irq, 102 .pic_reenable_irq = pi_enable_irq, 103 .pic_disable_irq = pi_disable_irq, 104 .pic_get_irq = pi_get_irq, 105 .pic_ack_irq = pi_ack_irq, 106 .pic_establish_irq = dummy_pic_establish_intr, 107 }; 108 109 void 110 pi_init_intr(void) 111 { 112 pic_irqmask = 0; 113 pic_actmask = 0; 114 115 /* Mask and clear all interrupts. */ 116 WR4(PI_INTMR, 0); 117 WR4(PI_INTSR, ~0U); 118 119 pic_add(&pic); 120 } 121