1 /* $NetBSD: rs5c316_mainbus.c,v 1.2 2012/01/21 19:44:29 nonaka Exp $ */ 2 3 /*- 4 * Copyright (C) 2009 NONAKA Kimihiro <nonaka (at) netbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: rs5c316_mainbus.c,v 1.2 2012/01/21 19:44:29 nonaka Exp $"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/device.h> 34 #include <sys/kernel.h> 35 36 #include <dev/clock_subr.h> 37 #include <dev/ic/rs5c313var.h> 38 39 #include <machine/autoconf.h> 40 41 #include <sh3/devreg.h> 42 #include <sh3/pfcreg.h> 43 44 #include <evbsh3/ap_ms104_sh4/ap_ms104_sh4reg.h> 45 #include <evbsh3/ap_ms104_sh4/ap_ms104_sh4var.h> 46 47 /* chip access methods */ 48 static void rtc_begin(struct rs5c313_softc *); 49 static void rtc_ce(struct rs5c313_softc *, int); 50 static void rtc_dir(struct rs5c313_softc *, int); 51 static void rtc_clk(struct rs5c313_softc *, int); 52 static int rtc_read(struct rs5c313_softc *); 53 static void rtc_write(struct rs5c313_softc *, int); 54 55 static struct rs5c313_ops rs5c316_mainbus_ops = { 56 .rs5c313_op_begin = rtc_begin, 57 .rs5c313_op_ce = rtc_ce, 58 .rs5c313_op_clk = rtc_clk, 59 .rs5c313_op_dir = rtc_dir, 60 .rs5c313_op_read = rtc_read, 61 .rs5c313_op_write = rtc_write, 62 }; 63 64 /* autoconf glue */ 65 static int rs5c316_mainbus_match(device_t, cfdata_t, void *); 66 static void rs5c316_mainbus_attach(device_t, device_t, void *); 67 68 CFATTACH_DECL_NEW(rs5c313_mainbus, sizeof(struct rs5c313_softc), 69 rs5c316_mainbus_match, rs5c316_mainbus_attach, NULL, NULL); 70 71 #define ndelay(x) delay(((x) + 999) / 1000) 72 73 static int 74 rs5c316_mainbus_match(device_t parent, cfdata_t cf, void *aux) 75 { 76 struct mainbus_attach_args *maa = (struct mainbus_attach_args *)aux; 77 78 if (strcmp(maa->ma_name, "rs5c313rtc") != 0) 79 return 0; 80 return 1; 81 } 82 83 84 static void 85 rs5c316_mainbus_attach(device_t parent, device_t self, void *aux) 86 { 87 struct rs5c313_softc *sc = device_private(self); 88 uint32_t reg; 89 90 sc->sc_dev = self; 91 sc->sc_model = MODEL_5C316; 92 sc->sc_ops = &rs5c316_mainbus_ops; 93 94 /* setup gpio pin */ 95 reg = _reg_read_4(SH4_PCTRA); 96 reg &= ~(3 << (GPIO_PIN_RTC_CE * 2)); 97 reg |= (1 << (GPIO_PIN_RTC_CE * 2)); /* output */ 98 reg &= ~(3 << (GPIO_PIN_RTC_SCLK * 2)); 99 reg |= (1 << (GPIO_PIN_RTC_SCLK * 2)); /* output */ 100 reg &= ~(3 << (GPIO_PIN_RTC_SIO * 2)); 101 reg |= (1 << (GPIO_PIN_RTC_SIO * 2)); /* output */ 102 _reg_write_4(SH4_PCTRA, reg); 103 104 rs5c313_attach(sc); 105 } 106 107 static void 108 rtc_begin(struct rs5c313_softc *sc) 109 { 110 111 /* nothing to do */ 112 } 113 114 static void 115 rtc_ce(struct rs5c313_softc *sc, int onoff) 116 { 117 uint16_t 118 119 reg = _reg_read_2(SH4_PDTRA); 120 if (onoff) { 121 reg |= (1 << GPIO_PIN_RTC_CE); 122 } else { 123 reg &= ~(1 << GPIO_PIN_RTC_CE); 124 } 125 _reg_write_2(SH4_PDTRA, reg); 126 ndelay(600); 127 } 128 129 static void 130 rtc_clk(struct rs5c313_softc *sc, int onoff) 131 { 132 uint16_t reg; 133 134 reg = _reg_read_2(SH4_PDTRA); 135 if (onoff) { 136 reg |= (1 << GPIO_PIN_RTC_SCLK); 137 } else { 138 reg &= ~(1 << GPIO_PIN_RTC_SCLK); 139 } 140 _reg_write_2(SH4_PDTRA, reg); 141 } 142 143 static void 144 rtc_dir(struct rs5c313_softc *sc, int output) 145 { 146 uint32_t reg; 147 148 reg = _reg_read_4(SH4_PCTRA); 149 reg &= ~(3 << (GPIO_PIN_RTC_SIO * 2)); /* input */ 150 if (output) { 151 reg |= (1 << (GPIO_PIN_RTC_SIO * 2)); /* output */ 152 } 153 _reg_write_4(SH4_PCTRA, reg); 154 } 155 156 static int 157 rtc_read(struct rs5c313_softc *sc) 158 { 159 int bit; 160 161 ndelay(300); 162 163 bit = (_reg_read_2(SH4_PDTRA) & (1 << GPIO_PIN_RTC_SIO)) ? 1 : 0; 164 165 rtc_clk(sc, 0); 166 ndelay(300); 167 rtc_clk(sc, 1); 168 169 return bit; 170 } 171 172 static void 173 rtc_write(struct rs5c313_softc *sc, int bit) 174 { 175 uint16_t reg; 176 177 reg = _reg_read_2(SH4_PDTRA); 178 if (bit) 179 reg |= (1 << GPIO_PIN_RTC_SIO); 180 else 181 reg &= ~(1 << GPIO_PIN_RTC_SIO); 182 _reg_write_2(SH4_PDTRA, reg); 183 184 ndelay(300); 185 186 rtc_clk(sc, 0); 187 ndelay(300); 188 rtc_clk(sc, 1); 189 } 190
Indexes created Sat Sep 20 22:09:52 GMT 2025