1 1.5 andvar /* -*-C++-*- $NetBSD: sh4.h,v 1.5 2025/06/28 07:04:52 andvar Exp $ */ 2 1.1 uch 3 1.1 uch /*- 4 1.1 uch * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.1 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.1 uch * by UCHIYAMA Yasushi. 9 1.1 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.1 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 uch * notice, this list of conditions and the following disclaimer in the 17 1.1 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.1 uch 32 1.1 uch #ifndef _HPCBOOT_SH_CPU_SH4_H_ 33 1.2 uch #define _HPCBOOT_SH_CPU_SH4_H_ 34 1.1 uch #include <sh3/cpu/sh.h> 35 1.1 uch 36 1.1 uch /* 37 1.1 uch * SH4 designed for Windows CE (SH7750) common defines. 38 1.1 uch */ 39 1.1 uch 40 1.2 uch #define SH4_TRA 0xff000020 41 1.2 uch #define SH4_EXPEVT 0xff000024 42 1.2 uch #define SH4_INTEVT 0xff000028 43 1.2 uch 44 1.2 uch #define SH4_ICR 0xffd00000 45 1.2 uch #define SH4_IPRA 0xffd00004 46 1.2 uch #define SH4_IPRB 0xffd00008 47 1.2 uch #define SH4_IPRC 0xffd0000c 48 1.2 uch #define SH4_IPRD 0xffd00010 49 1.1 uch 50 1.1 uch /* Windows CE uses 1Kbyte page for SH3, 4Kbyte for SH4 */ 51 1.2 uch #define SH4_PAGE_SIZE 0x1000 52 1.2 uch #define SH4_PAGE_MASK (~(SH4_PAGE_SIZE - 1)) 53 1.1 uch 54 1.1 uch /* 55 1.1 uch * Cache 56 1.1 uch */ 57 1.2 uch #define SH4_ICACHE_SIZE 8192 58 1.2 uch #define SH4_DCACHE_SIZE 16384 59 1.2 uch #define SH4_CACHE_LINESZ 32 60 1.2 uch 61 1.2 uch #define SH4_CCR 0xff00001c 62 1.2 uch #define SH4_CCR_IIX 0x00008000 63 1.2 uch #define SH4_CCR_ICI 0x00000800 64 1.2 uch #define SH4_CCR_ICE 0x00000100 65 1.2 uch #define SH4_CCR_OIX 0x00000080 66 1.2 uch #define SH4_CCR_ORA 0x00000020 67 1.2 uch #define SH4_CCR_OCI 0x00000008 68 1.2 uch #define SH4_CCR_CB 0x00000004 69 1.2 uch #define SH4_CCR_WT 0x00000002 70 1.2 uch #define SH4_CCR_OCE 0x00000001 71 1.2 uch 72 1.2 uch #define SH4_QACR0 0xff000038 73 1.2 uch #define SH4_QACR1 0xff00003c 74 1.2 uch #define SH4_QACR_AREA_SHIFT 2 75 1.2 uch #define SH4_QACR_AREA_MASK 0x0000001c 76 1.1 uch 77 1.1 uch /* I-cache address/data array */ 78 1.2 uch #define SH4REG_CCIA 0xf0000000 79 1.1 uch /* address specification */ 80 1.2 uch #define CCIA_A 0x00000008 /* associate bit */ 81 1.2 uch #define CCIA_ENTRY_SHIFT 5 /* line size 32B */ 82 1.2 uch #define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 83 1.1 uch /* data specification */ 84 1.2 uch #define CCIA_V 0x00000001 85 1.2 uch #define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 86 1.1 uch 87 1.2 uch #define SH4REG_CCID 0xf1000000 88 1.1 uch /* address specification */ 89 1.2 uch #define CCID_L_SHIFT 2 90 1.2 uch #define CCID_L_MASK 0x1c /* line-size is 32B */ 91 1.2 uch #define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 128-entries */ 92 1.1 uch 93 1.1 uch /* D-cache address/data array */ 94 1.2 uch #define SH4REG_CCDA 0xf4000000 95 1.1 uch /* address specification */ 96 1.2 uch #define CCDA_A 0x00000008 /* associate bit */ 97 1.2 uch #define CCDA_ENTRY_SHIFT 5 /* line size 32B */ 98 1.2 uch #define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 99 1.1 uch /* data specification */ 100 1.2 uch #define CCDA_V 0x00000001 101 1.2 uch #define CCDA_U 0x00000002 102 1.2 uch #define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 103 1.1 uch 104 1.2 uch #define SH4REG_CCDD 0xf5000000 105 1.1 uch 106 1.1 uch /* 107 1.1 uch * MMU 108 1.1 uch */ 109 1.2 uch #define SH4_PTEH 0xff000000 110 1.2 uch #define SH4_PTEH_ASID_MASK 0x0000000f 111 1.2 uch #define SH4_PTEL 0xff000004 112 1.2 uch #define SH4_PTEL_WT 0x00000001 113 1.2 uch #define SH4_PTEL_SH 0x00000002 114 1.2 uch #define SH4_PTEL_D 0x00000004 115 1.2 uch #define SH4_PTEL_C 0x00000008 116 1.2 uch #define SH4_PTEL_PR_SHIFT 5 117 1.2 uch #define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */ 118 1.2 uch #define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */ 119 1.2 uch #define SH4_PTEL_SZ_1K 0x00000000 120 1.2 uch #define SH4_PTEL_SZ_4K 0x00000010 121 1.2 uch #define SH4_PTEL_SZ_64K 0x00000080 122 1.2 uch #define SH4_PTEL_SZ_1M 0x00000090 123 1.2 uch #define SH4_PTEL_V 0x00000100 124 1.2 uch #define SH4_PTEA 0xff000034 125 1.2 uch #define SH4_PTEA_SA_MASK 0x00000007 126 1.2 uch #define SH4_PTEA_SA_TC 0x00000008 127 1.2 uch #define SH4_TTB 0xff000008 128 1.2 uch #define SH4_TTA 0xff00000c 129 1.2 uch #define SH4_MMUCR 0xff000010 130 1.2 uch #define SH4_MMUCR_AT 0x00000001 131 1.2 uch #define SH4_MMUCR_TI 0x00000004 132 1.2 uch #define SH4_MMUCR_SV 0x00000100 133 1.2 uch #define SH4_MMUCR_SQMD 0x00000200 134 1.2 uch #define SH4_MMUCR_URC_SHIFT 10 135 1.2 uch #define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */ 136 1.2 uch #define SH4_MMUCR_URB_SHIFT 18 137 1.2 uch #define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */ 138 1.2 uch #define SH4_MMUCR_LRUI_SHIFT 26 139 1.2 uch #define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */ 140 1.2 uch /* 141 1.2 uch * memory-mapped TLB 142 1.5 andvar * must be accessed from P2-area program. 143 1.5 andvar * branch to the other area must be made at least 8 instructions 144 1.1 uch * after access. 145 1.1 uch */ 146 1.1 uch /* ITLB */ 147 1.2 uch #define SH4_ITLB_AA 0xf2000000 148 1.1 uch /* address specification (common for address and data array(0,1)) */ 149 1.2 uch #define SH4_ITLB_E_SHIFT 8 150 1.2 uch #define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */ 151 1.1 uch /* data specification */ 152 1.1 uch /* address-array */ 153 1.2 uch #define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 154 1.2 uch #define SH4_ITLB_AA_V 0x00000100 155 1.2 uch #define SH4_ITLB_AA_VPN_SHIFT 10 156 1.2 uch #define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 157 1.1 uch /* data-array 1 */ 158 1.2 uch #define SH4_ITLB_DA1 0xf3000000 159 1.2 uch #define SH4_ITLB_DA1_SH 0x00000002 160 1.2 uch #define SH4_ITLB_DA1_C 0x00000008 161 1.2 uch #define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 162 1.2 uch #define SH4_ITLB_DA1_SZ_1K 0x00000000 163 1.2 uch #define SH4_ITLB_DA1_SZ_4K 0x00000010 164 1.2 uch #define SH4_ITLB_DA1_SZ_64K 0x00000080 165 1.2 uch #define SH4_ITLB_DA1_SZ_1M 0x00000090 166 1.2 uch #define SH4_ITLB_DA1_PR 0x00000040 167 1.2 uch #define SH4_ITLB_DA1_V 0x00000100 168 1.2 uch #define SH4_ITLB_DA1_PPN_SHIFT 11 169 1.2 uch #define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 170 1.1 uch /* data-array 2 */ 171 1.2 uch #define SH4_ITLB_DA2 0xf3800000 172 1.2 uch #define SH4_ITLB_DA2_SA_MASK 0x00000003 173 1.2 uch #define SH4_ITLB_DA2_TC 0x00000004 174 1.1 uch 175 1.1 uch /* UTLB */ 176 1.2 uch #define SH4_UTLB_AA 0xf6000000 177 1.1 uch /* address specification (common for address and data array(0,1)) */ 178 1.2 uch #define SH4_UTLB_E_SHIFT 8 179 1.2 uch #define SH4_UTLB_E_MASK 0x00003f00 180 1.1 uch /* data specification */ 181 1.1 uch /* address-array */ 182 1.2 uch #define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 183 1.2 uch #define SH4_UTLB_AA_D 0x00000200 184 1.2 uch #define SH4_UTLB_AA_V 0x00000100 185 1.2 uch #define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 186 1.1 uch /* data-array 1 */ 187 1.2 uch #define SH4_UTLB_DA1 0xf7000000 188 1.2 uch #define SH4_UTLB_DA1_WT 0x00000001 189 1.2 uch #define SH4_UTLB_DA1_SH 0x00000002 190 1.2 uch #define SH4_UTLB_DA1_D 0x00000004 191 1.2 uch #define SH4_UTLB_DA1_C 0x00000008 192 1.2 uch #define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 193 1.2 uch #define SH4_UTLB_DA1_SZ_1K 0x00000000 194 1.2 uch #define SH4_UTLB_DA1_SZ_4K 0x00000010 195 1.2 uch #define SH4_UTLB_DA1_SZ_64K 0x00000080 196 1.2 uch #define SH4_UTLB_DA1_SZ_1M 0x00000090 197 1.2 uch #define SH4_UTLB_DA1_PR_SHIFT 5 198 1.2 uch #define SH4_UTLB_DA1_PR_MASK 0x00000060 199 1.2 uch #define SH4_UTLB_DA1_V 0x00000100 200 1.2 uch #define SH4_UTLB_DA1_PPN_SHIFT 11 201 1.2 uch #define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 202 1.1 uch /* data-array 2 */ 203 1.2 uch #define SH4_UTLB_DA2 0xf7800000 204 1.2 uch #define SH4_UTLB_DA2_SA_MASK 0x00000003 205 1.2 uch #define SH4_UTLB_DA2_TC 0x00000004 206 1.1 uch 207 1.2 uch #define SH4_MMU_DISABLE() _reg_write_4(SH4_MMUCR, SH4_MMUCR_TI) 208 1.1 uch 209 1.2 uch /* 210 1.1 uch * Product dependent headers 211 1.1 uch */ 212 1.1 uch #include <sh3/cpu/7750.h> 213 1.1 uch 214 1.1 uch #endif /* _HPCBOOT_SH_CPU_SH4_H_ */ 215
Indexes created Mon Sep 22 13:09:51 GMT 2025