1 /* -*-C++-*- $NetBSD: sh4.h,v 1.5 2025/06/28 07:04:52 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _HPCBOOT_SH_CPU_SH4_H_ 33 #define _HPCBOOT_SH_CPU_SH4_H_ 34 #include <sh3/cpu/sh.h> 35 36 /* 37 * SH4 designed for Windows CE (SH7750) common defines. 38 */ 39 40 #define SH4_TRA 0xff000020 41 #define SH4_EXPEVT 0xff000024 42 #define SH4_INTEVT 0xff000028 43 44 #define SH4_ICR 0xffd00000 45 #define SH4_IPRA 0xffd00004 46 #define SH4_IPRB 0xffd00008 47 #define SH4_IPRC 0xffd0000c 48 #define SH4_IPRD 0xffd00010 49 50 /* Windows CE uses 1Kbyte page for SH3, 4Kbyte for SH4 */ 51 #define SH4_PAGE_SIZE 0x1000 52 #define SH4_PAGE_MASK (~(SH4_PAGE_SIZE - 1)) 53 54 /* 55 * Cache 56 */ 57 #define SH4_ICACHE_SIZE 8192 58 #define SH4_DCACHE_SIZE 16384 59 #define SH4_CACHE_LINESZ 32 60 61 #define SH4_CCR 0xff00001c 62 #define SH4_CCR_IIX 0x00008000 63 #define SH4_CCR_ICI 0x00000800 64 #define SH4_CCR_ICE 0x00000100 65 #define SH4_CCR_OIX 0x00000080 66 #define SH4_CCR_ORA 0x00000020 67 #define SH4_CCR_OCI 0x00000008 68 #define SH4_CCR_CB 0x00000004 69 #define SH4_CCR_WT 0x00000002 70 #define SH4_CCR_OCE 0x00000001 71 72 #define SH4_QACR0 0xff000038 73 #define SH4_QACR1 0xff00003c 74 #define SH4_QACR_AREA_SHIFT 2 75 #define SH4_QACR_AREA_MASK 0x0000001c 76 77 /* I-cache address/data array */ 78 #define SH4REG_CCIA 0xf0000000 79 /* address specification */ 80 #define CCIA_A 0x00000008 /* associate bit */ 81 #define CCIA_ENTRY_SHIFT 5 /* line size 32B */ 82 #define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 83 /* data specification */ 84 #define CCIA_V 0x00000001 85 #define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 86 87 #define SH4REG_CCID 0xf1000000 88 /* address specification */ 89 #define CCID_L_SHIFT 2 90 #define CCID_L_MASK 0x1c /* line-size is 32B */ 91 #define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 128-entries */ 92 93 /* D-cache address/data array */ 94 #define SH4REG_CCDA 0xf4000000 95 /* address specification */ 96 #define CCDA_A 0x00000008 /* associate bit */ 97 #define CCDA_ENTRY_SHIFT 5 /* line size 32B */ 98 #define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 99 /* data specification */ 100 #define CCDA_V 0x00000001 101 #define CCDA_U 0x00000002 102 #define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 103 104 #define SH4REG_CCDD 0xf5000000 105 106 /* 107 * MMU 108 */ 109 #define SH4_PTEH 0xff000000 110 #define SH4_PTEH_ASID_MASK 0x0000000f 111 #define SH4_PTEL 0xff000004 112 #define SH4_PTEL_WT 0x00000001 113 #define SH4_PTEL_SH 0x00000002 114 #define SH4_PTEL_D 0x00000004 115 #define SH4_PTEL_C 0x00000008 116 #define SH4_PTEL_PR_SHIFT 5 117 #define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */ 118 #define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */ 119 #define SH4_PTEL_SZ_1K 0x00000000 120 #define SH4_PTEL_SZ_4K 0x00000010 121 #define SH4_PTEL_SZ_64K 0x00000080 122 #define SH4_PTEL_SZ_1M 0x00000090 123 #define SH4_PTEL_V 0x00000100 124 #define SH4_PTEA 0xff000034 125 #define SH4_PTEA_SA_MASK 0x00000007 126 #define SH4_PTEA_SA_TC 0x00000008 127 #define SH4_TTB 0xff000008 128 #define SH4_TTA 0xff00000c 129 #define SH4_MMUCR 0xff000010 130 #define SH4_MMUCR_AT 0x00000001 131 #define SH4_MMUCR_TI 0x00000004 132 #define SH4_MMUCR_SV 0x00000100 133 #define SH4_MMUCR_SQMD 0x00000200 134 #define SH4_MMUCR_URC_SHIFT 10 135 #define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */ 136 #define SH4_MMUCR_URB_SHIFT 18 137 #define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */ 138 #define SH4_MMUCR_LRUI_SHIFT 26 139 #define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */ 140 /* 141 * memory-mapped TLB 142 * must be accessed from P2-area program. 143 * branch to the other area must be made at least 8 instructions 144 * after access. 145 */ 146 /* ITLB */ 147 #define SH4_ITLB_AA 0xf2000000 148 /* address specification (common for address and data array(0,1)) */ 149 #define SH4_ITLB_E_SHIFT 8 150 #define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */ 151 /* data specification */ 152 /* address-array */ 153 #define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 154 #define SH4_ITLB_AA_V 0x00000100 155 #define SH4_ITLB_AA_VPN_SHIFT 10 156 #define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 157 /* data-array 1 */ 158 #define SH4_ITLB_DA1 0xf3000000 159 #define SH4_ITLB_DA1_SH 0x00000002 160 #define SH4_ITLB_DA1_C 0x00000008 161 #define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 162 #define SH4_ITLB_DA1_SZ_1K 0x00000000 163 #define SH4_ITLB_DA1_SZ_4K 0x00000010 164 #define SH4_ITLB_DA1_SZ_64K 0x00000080 165 #define SH4_ITLB_DA1_SZ_1M 0x00000090 166 #define SH4_ITLB_DA1_PR 0x00000040 167 #define SH4_ITLB_DA1_V 0x00000100 168 #define SH4_ITLB_DA1_PPN_SHIFT 11 169 #define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 170 /* data-array 2 */ 171 #define SH4_ITLB_DA2 0xf3800000 172 #define SH4_ITLB_DA2_SA_MASK 0x00000003 173 #define SH4_ITLB_DA2_TC 0x00000004 174 175 /* UTLB */ 176 #define SH4_UTLB_AA 0xf6000000 177 /* address specification (common for address and data array(0,1)) */ 178 #define SH4_UTLB_E_SHIFT 8 179 #define SH4_UTLB_E_MASK 0x00003f00 180 /* data specification */ 181 /* address-array */ 182 #define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 183 #define SH4_UTLB_AA_D 0x00000200 184 #define SH4_UTLB_AA_V 0x00000100 185 #define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 186 /* data-array 1 */ 187 #define SH4_UTLB_DA1 0xf7000000 188 #define SH4_UTLB_DA1_WT 0x00000001 189 #define SH4_UTLB_DA1_SH 0x00000002 190 #define SH4_UTLB_DA1_D 0x00000004 191 #define SH4_UTLB_DA1_C 0x00000008 192 #define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 193 #define SH4_UTLB_DA1_SZ_1K 0x00000000 194 #define SH4_UTLB_DA1_SZ_4K 0x00000010 195 #define SH4_UTLB_DA1_SZ_64K 0x00000080 196 #define SH4_UTLB_DA1_SZ_1M 0x00000090 197 #define SH4_UTLB_DA1_PR_SHIFT 5 198 #define SH4_UTLB_DA1_PR_MASK 0x00000060 199 #define SH4_UTLB_DA1_V 0x00000100 200 #define SH4_UTLB_DA1_PPN_SHIFT 11 201 #define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 202 /* data-array 2 */ 203 #define SH4_UTLB_DA2 0xf7800000 204 #define SH4_UTLB_DA2_SA_MASK 0x00000003 205 #define SH4_UTLB_DA2_TC 0x00000004 206 207 #define SH4_MMU_DISABLE() _reg_write_4(SH4_MMUCR, SH4_MMUCR_TI) 208 209 /* 210 * Product dependent headers 211 */ 212 #include <sh3/cpu/7750.h> 213 214 #endif /* _HPCBOOT_SH_CPU_SH4_H_ */ 215
Indexes created Sat Sep 20 22:09:52 GMT 2025