sh4.h revision 1.1.2.2
1 1.1.2.2 nathanw /* -*-C++-*- $NetBSD: sh4.h,v 1.1.2.2 2002/02/28 04:09:47 nathanw Exp $ */ 2 1.1.2.2 nathanw 3 1.1.2.2 nathanw /*- 4 1.1.2.2 nathanw * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 1.1.2.2 nathanw * All rights reserved. 6 1.1.2.2 nathanw * 7 1.1.2.2 nathanw * This code is derived from software contributed to The NetBSD Foundation 8 1.1.2.2 nathanw * by UCHIYAMA Yasushi. 9 1.1.2.2 nathanw * 10 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 11 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 12 1.1.2.2 nathanw * are met: 13 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 14 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 15 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 16 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 17 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 18 1.1.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 19 1.1.2.2 nathanw * must display the following acknowledgement: 20 1.1.2.2 nathanw * This product includes software developed by the NetBSD 21 1.1.2.2 nathanw * Foundation, Inc. and its contributors. 22 1.1.2.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.1.2.2 nathanw * contributors may be used to endorse or promote products derived 24 1.1.2.2 nathanw * from this software without specific prior written permission. 25 1.1.2.2 nathanw * 26 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.1.2.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.1.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.1.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.1.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.1.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.1.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.1.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.1.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.1.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.1.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 37 1.1.2.2 nathanw */ 38 1.1.2.2 nathanw 39 1.1.2.2 nathanw #ifndef _HPCBOOT_SH_CPU_SH4_H_ 40 1.1.2.2 nathanw #define _HPCBOOT_SH_CPU_SH4_H_ 41 1.1.2.2 nathanw #include <sh3/cpu/sh.h> 42 1.1.2.2 nathanw 43 1.1.2.2 nathanw /* 44 1.1.2.2 nathanw * SH4 designed for Windows CE (SH7750) common defines. 45 1.1.2.2 nathanw */ 46 1.1.2.2 nathanw 47 1.1.2.2 nathanw #define SH4_TRA 0xff000020 48 1.1.2.2 nathanw #define SH4_EXPEVT 0xff000024 49 1.1.2.2 nathanw #define SH4_INTEVT 0xff000028 50 1.1.2.2 nathanw 51 1.1.2.2 nathanw #define SH4_ICR 0xffd00000 52 1.1.2.2 nathanw #define SH4_IPRA 0xffd00004 53 1.1.2.2 nathanw #define SH4_IPRB 0xffd00008 54 1.1.2.2 nathanw #define SH4_IPRC 0xffd0000c 55 1.1.2.2 nathanw #define SH4_IPRD 0xffd00010 56 1.1.2.2 nathanw 57 1.1.2.2 nathanw /* Windows CE uses 1Kbyte page for SH3, 4Kbyte for SH4 */ 58 1.1.2.2 nathanw #define SH4_PAGE_SIZE 0x1000 59 1.1.2.2 nathanw #define SH4_PAGE_MASK (~(SH4_PAGE_SIZE - 1)) 60 1.1.2.2 nathanw 61 1.1.2.2 nathanw /* 62 1.1.2.2 nathanw * Cache 63 1.1.2.2 nathanw */ 64 1.1.2.2 nathanw #define SH4_ICACHE_SIZE 8192 65 1.1.2.2 nathanw #define SH4_DCACHE_SIZE 16384 66 1.1.2.2 nathanw #define SH4_CACHE_LINESZ 32 67 1.1.2.2 nathanw 68 1.1.2.2 nathanw #define SH4_CCR 0xff00001c 69 1.1.2.2 nathanw #define SH4_CCR_IIX 0x00008000 70 1.1.2.2 nathanw #define SH4_CCR_ICI 0x00000800 71 1.1.2.2 nathanw #define SH4_CCR_ICE 0x00000100 72 1.1.2.2 nathanw #define SH4_CCR_OIX 0x00000080 73 1.1.2.2 nathanw #define SH4_CCR_ORA 0x00000020 74 1.1.2.2 nathanw #define SH4_CCR_OCI 0x00000008 75 1.1.2.2 nathanw #define SH4_CCR_CB 0x00000004 76 1.1.2.2 nathanw #define SH4_CCR_WT 0x00000002 77 1.1.2.2 nathanw #define SH4_CCR_OCE 0x00000001 78 1.1.2.2 nathanw 79 1.1.2.2 nathanw #define SH4_QACR0 0xff000038 80 1.1.2.2 nathanw #define SH4_QACR1 0xff00003c 81 1.1.2.2 nathanw #define SH4_QACR_AREA_SHIFT 2 82 1.1.2.2 nathanw #define SH4_QACR_AREA_MASK 0x0000001c 83 1.1.2.2 nathanw 84 1.1.2.2 nathanw /* I-cache address/data array */ 85 1.1.2.2 nathanw #define SH4REG_CCIA 0xf0000000 86 1.1.2.2 nathanw /* address specification */ 87 1.1.2.2 nathanw #define CCIA_A 0x00000008 /* associate bit */ 88 1.1.2.2 nathanw #define CCIA_ENTRY_SHIFT 5 /* line size 32B */ 89 1.1.2.2 nathanw #define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 90 1.1.2.2 nathanw /* data specification */ 91 1.1.2.2 nathanw #define CCIA_V 0x00000001 92 1.1.2.2 nathanw #define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 93 1.1.2.2 nathanw 94 1.1.2.2 nathanw #define SH4REG_CCID 0xf1000000 95 1.1.2.2 nathanw /* address specification */ 96 1.1.2.2 nathanw #define CCID_L_SHIFT 2 97 1.1.2.2 nathanw #define CCID_L_MASK 0x1c /* line-size is 32B */ 98 1.1.2.2 nathanw #define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 128-entries */ 99 1.1.2.2 nathanw 100 1.1.2.2 nathanw /* D-cache address/data array */ 101 1.1.2.2 nathanw #define SH4REG_CCDA 0xf4000000 102 1.1.2.2 nathanw /* address specification */ 103 1.1.2.2 nathanw #define CCDA_A 0x00000008 /* associate bit */ 104 1.1.2.2 nathanw #define CCDA_ENTRY_SHIFT 5 /* line size 32B */ 105 1.1.2.2 nathanw #define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 106 1.1.2.2 nathanw /* data specification */ 107 1.1.2.2 nathanw #define CCDA_V 0x00000001 108 1.1.2.2 nathanw #define CCDA_U 0x00000002 109 1.1.2.2 nathanw #define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 110 1.1.2.2 nathanw 111 1.1.2.2 nathanw #define SH4REG_CCDD 0xf5000000 112 1.1.2.2 nathanw 113 1.1.2.2 nathanw /* 114 1.1.2.2 nathanw * MMU 115 1.1.2.2 nathanw */ 116 1.1.2.2 nathanw #define SH4_PTEH 0xff000000 117 1.1.2.2 nathanw #define SH4_PTEH_ASID_MASK 0x0000000f 118 1.1.2.2 nathanw #define SH4_PTEL 0xff000004 119 1.1.2.2 nathanw #define SH4_PTEL_WT 0x00000001 120 1.1.2.2 nathanw #define SH4_PTEL_SH 0x00000002 121 1.1.2.2 nathanw #define SH4_PTEL_D 0x00000004 122 1.1.2.2 nathanw #define SH4_PTEL_C 0x00000008 123 1.1.2.2 nathanw #define SH4_PTEL_PR_SHIFT 5 124 1.1.2.2 nathanw #define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */ 125 1.1.2.2 nathanw #define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */ 126 1.1.2.2 nathanw #define SH4_PTEL_SZ_1K 0x00000000 127 1.1.2.2 nathanw #define SH4_PTEL_SZ_4K 0x00000010 128 1.1.2.2 nathanw #define SH4_PTEL_SZ_64K 0x00000080 129 1.1.2.2 nathanw #define SH4_PTEL_SZ_1M 0x00000090 130 1.1.2.2 nathanw #define SH4_PTEL_V 0x00000100 131 1.1.2.2 nathanw #define SH4_PTEA 0xff000034 132 1.1.2.2 nathanw #define SH4_PTEA_SA_MASK 0x00000007 133 1.1.2.2 nathanw #define SH4_PTEA_SA_TC 0x00000008 134 1.1.2.2 nathanw #define SH4_TTB 0xff000008 135 1.1.2.2 nathanw #define SH4_TTA 0xff00000c 136 1.1.2.2 nathanw #define SH4_MMUCR 0xff000010 137 1.1.2.2 nathanw #define SH4_MMUCR_AT 0x00000001 138 1.1.2.2 nathanw #define SH4_MMUCR_TI 0x00000004 139 1.1.2.2 nathanw #define SH4_MMUCR_SV 0x00000100 140 1.1.2.2 nathanw #define SH4_MMUCR_SQMD 0x00000200 141 1.1.2.2 nathanw #define SH4_MMUCR_URC_SHIFT 10 142 1.1.2.2 nathanw #define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */ 143 1.1.2.2 nathanw #define SH4_MMUCR_URB_SHIFT 18 144 1.1.2.2 nathanw #define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */ 145 1.1.2.2 nathanw #define SH4_MMUCR_LRUI_SHIFT 26 146 1.1.2.2 nathanw #define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */ 147 1.1.2.2 nathanw /* 148 1.1.2.2 nathanw * memory-mapped TLB 149 1.1.2.2 nathanw * must be access from P2-area program. 150 1.1.2.2 nathanw * branch to the other area must be maed at least 8 instruction 151 1.1.2.2 nathanw * after access. 152 1.1.2.2 nathanw */ 153 1.1.2.2 nathanw /* ITLB */ 154 1.1.2.2 nathanw #define SH4_ITLB_AA 0xf2000000 155 1.1.2.2 nathanw /* address specification (common for address and data array(0,1)) */ 156 1.1.2.2 nathanw #define SH4_ITLB_E_SHIFT 8 157 1.1.2.2 nathanw #define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */ 158 1.1.2.2 nathanw /* data specification */ 159 1.1.2.2 nathanw /* address-array */ 160 1.1.2.2 nathanw #define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 161 1.1.2.2 nathanw #define SH4_ITLB_AA_V 0x00000100 162 1.1.2.2 nathanw #define SH4_ITLB_AA_VPN_SHIFT 10 163 1.1.2.2 nathanw #define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 164 1.1.2.2 nathanw /* data-array 1 */ 165 1.1.2.2 nathanw #define SH4_ITLB_DA1 0xf3000000 166 1.1.2.2 nathanw #define SH4_ITLB_DA1_SH 0x00000002 167 1.1.2.2 nathanw #define SH4_ITLB_DA1_C 0x00000008 168 1.1.2.2 nathanw #define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 169 1.1.2.2 nathanw #define SH4_ITLB_DA1_SZ_1K 0x00000000 170 1.1.2.2 nathanw #define SH4_ITLB_DA1_SZ_4K 0x00000010 171 1.1.2.2 nathanw #define SH4_ITLB_DA1_SZ_64K 0x00000080 172 1.1.2.2 nathanw #define SH4_ITLB_DA1_SZ_1M 0x00000090 173 1.1.2.2 nathanw #define SH4_ITLB_DA1_PR 0x00000040 174 1.1.2.2 nathanw #define SH4_ITLB_DA1_V 0x00000100 175 1.1.2.2 nathanw #define SH4_ITLB_DA1_PPN_SHIFT 11 176 1.1.2.2 nathanw #define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 177 1.1.2.2 nathanw /* data-array 2 */ 178 1.1.2.2 nathanw #define SH4_ITLB_DA2 0xf3800000 179 1.1.2.2 nathanw #define SH4_ITLB_DA2_SA_MASK 0x00000003 180 1.1.2.2 nathanw #define SH4_ITLB_DA2_TC 0x00000004 181 1.1.2.2 nathanw 182 1.1.2.2 nathanw /* UTLB */ 183 1.1.2.2 nathanw #define SH4_UTLB_AA 0xf6000000 184 1.1.2.2 nathanw /* address specification (common for address and data array(0,1)) */ 185 1.1.2.2 nathanw #define SH4_UTLB_E_SHIFT 8 186 1.1.2.2 nathanw #define SH4_UTLB_E_MASK 0x00003f00 187 1.1.2.2 nathanw /* data specification */ 188 1.1.2.2 nathanw /* address-array */ 189 1.1.2.2 nathanw #define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */ 190 1.1.2.2 nathanw #define SH4_UTLB_AA_D 0x00000200 191 1.1.2.2 nathanw #define SH4_UTLB_AA_V 0x00000100 192 1.1.2.2 nathanw #define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */ 193 1.1.2.2 nathanw /* data-array 1 */ 194 1.1.2.2 nathanw #define SH4_UTLB_DA1 0xf7000000 195 1.1.2.2 nathanw #define SH4_UTLB_DA1_WT 0x00000001 196 1.1.2.2 nathanw #define SH4_UTLB_DA1_SH 0x00000002 197 1.1.2.2 nathanw #define SH4_UTLB_DA1_D 0x00000004 198 1.1.2.2 nathanw #define SH4_UTLB_DA1_C 0x00000008 199 1.1.2.2 nathanw #define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */ 200 1.1.2.2 nathanw #define SH4_UTLB_DA1_SZ_1K 0x00000000 201 1.1.2.2 nathanw #define SH4_UTLB_DA1_SZ_4K 0x00000010 202 1.1.2.2 nathanw #define SH4_UTLB_DA1_SZ_64K 0x00000080 203 1.1.2.2 nathanw #define SH4_UTLB_DA1_SZ_1M 0x00000090 204 1.1.2.2 nathanw #define SH4_UTLB_DA1_PR_SHIFT 5 205 1.1.2.2 nathanw #define SH4_UTLB_DA1_PR_MASK 0x00000060 206 1.1.2.2 nathanw #define SH4_UTLB_DA1_V 0x00000100 207 1.1.2.2 nathanw #define SH4_UTLB_DA1_PPN_SHIFT 11 208 1.1.2.2 nathanw #define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */ 209 1.1.2.2 nathanw /* data-array 2 */ 210 1.1.2.2 nathanw #define SH4_UTLB_DA2 0xf7800000 211 1.1.2.2 nathanw #define SH4_UTLB_DA2_SA_MASK 0x00000003 212 1.1.2.2 nathanw #define SH4_UTLB_DA2_TC 0x00000004 213 1.1.2.2 nathanw 214 1.1.2.2 nathanw #define SH4_MMU_DISABLE() _reg_write_4(SH4_MMUCR, SH4_MMUCR_TI) 215 1.1.2.2 nathanw 216 1.1.2.2 nathanw /* 217 1.1.2.2 nathanw * Product dependent headers 218 1.1.2.2 nathanw */ 219 1.1.2.2 nathanw #include <sh3/cpu/7750.h> 220 1.1.2.2 nathanw 221 1.1.2.2 nathanw #endif /* _HPCBOOT_SH_CPU_SH4_H_ */ 222
Indexes created Wed Oct 01 07:09:59 GMT 2025