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      1 /* -*-C++-*-	$NetBSD: sh4_dev.cpp,v 1.5 2008/04/28 20:23:20 martin Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by UCHIYAMA Yasushi.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <hpcboot.h>
     33 #include <hpcmenu.h>
     34 #include <console.h>
     35 
     36 #include <sh3/sh_arch.h> //suspend/resumeIntr
     37 
     38 #include <sh3/cpu/sh4.h>
     39 #include <sh3/dev/sh_dev.h>
     40 
     41 #include <sh3/dev/sh.h>
     42 #include <sh3/dev/hd64465.h>
     43 #include <sh3/dev/mq100.h>
     44 
     45 struct SH4dev::intr_priority SH4dev::_ipr_table[] = {
     46 	// SH7750, SH7750S
     47 	{ "TMU0",	SH4_IPRA, 12 },
     48 	{ "TMU1",	SH4_IPRA,  8 },
     49 	{ "TMU2",	SH4_IPRA,  4 },
     50 	{ "RTC",	SH4_IPRA,  0 },
     51 	{ "WDT",	SH4_IPRB, 12 },
     52 	{ "REF",	SH4_IPRB,  8 },
     53 	{ "SCI",	SH4_IPRB,  4 },
     54 	{ "reserve",	SH4_IPRB,  0 },
     55 	{ "GPIO",	SH4_IPRC, 12 },
     56 	{ "DMAC",	SH4_IPRC,  8 },
     57 	{ "SCIF",	SH4_IPRC,  4 },
     58 	{ "H-UDI",	SH4_IPRC,  0 },
     59 	// SH7750S
     60 	{ "IRL0",	SH4_IPRD, 12 },
     61 	{ "IRL1",	SH4_IPRD,  8 },
     62 	{ "IRL2",	SH4_IPRD,  4 },
     63 	{ "IRL3",	SH4_IPRD,  0 },
     64 	{ 0, 0, 0} /* terminator */
     65 };
     66 
     67 void
     68 SH4dev::dump(uint8_t bit)
     69 {
     70 	int kmode;
     71 
     72 	super::dump(bit);
     73 
     74 	kmode = SetKMode(1);
     75 	if (bit & DUMP_DEV) {
     76 		// INTC
     77 		icu_dump();
     78 	}
     79 
     80 	if (bit & DUMP_COMPANION) {
     81 		// HD64465
     82 		hd64465_dump();
     83 	}
     84 
     85 	if (bit & DUMP_VIDEO) {
     86 		// MQ100
     87 		mq100_dump();
     88 	}
     89 
     90 	SetKMode(kmode);
     91 
     92 }
     93 
     94 // INTC
     95 void
     96 SH4dev::icu_dump()
     97 {
     98 #define	ON(x, c)	((x) & (c) ? check[1] : check[0])
     99 #define	_(n)		DPRINTF((TEXT("%S %S "), #n, ON(r, SH4_ICR_ ## n)))
    100 	static const char *check[] = { "[_]", "[x]" };
    101 	uint16_t r;
    102 
    103 	super::icu_dump_priority(_ipr_table);
    104 
    105 	r = _reg_read_2(SH4_ICR);
    106 	DPRINTF((TEXT("ICR: ")));
    107 	_(NMIL);_(MAI);_(NMIB);_(NMIE);_(IRLM);
    108 	DPRINTF((TEXT("0x%04x\n"), r));
    109 
    110 #if 0 // monitoring SH4 interrupt request.
    111 	// disable SH3 internal devices interrupt.
    112 	suspendIntr();
    113 	_reg_write_2(SH4_IPRA, 0);
    114 	_reg_write_2(SH4_IPRB, 0);
    115 	_reg_write_2(SH4_IPRC, 0);
    116 //	_reg_write_2(SH4_IPRD, 0);  SH7709S only.
    117 	resumeIntr(0);	// all interrupts enable.
    118 	while (1) {
    119 		DPRINTF((TEXT("%04x ", _reg_read_2(HD64465_NIRR))));
    120 		bitdisp(_reg_read_4(SH4_INTEVT));
    121 	}
    122 	/* NOTREACHED */
    123 #endif
    124 #undef _
    125 #undef ON
    126 }
    127 
    128 void
    129 SH4dev::hd64465_dump()
    130 {
    131 
    132 	DPRINTF((TEXT("<<<HD64465>>>\n")));
    133 	if (_reg_read_2(HD64465_SDIDR) != 0x8122) {
    134 		DPRINTF((TEXT("not found.\n")));
    135 		return;
    136 	}
    137 
    138 	DPRINTF((TEXT("SMSCR:  ")));	// standby
    139 	bitdisp(_reg_read_2(HD64465_SMSCR));
    140 	DPRINTF((TEXT("SPCCR:  ")));	// clock
    141 	bitdisp(_reg_read_2(HD64465_SPCCR));
    142 
    143 	DPRINTF((TEXT("\nNIRR:   ")));	// request
    144 	bitdisp(_reg_read_2(HD64465_NIRR));
    145 	DPRINTF((TEXT("NIMR:   ")));	// mask
    146 	bitdisp(_reg_read_2(HD64465_NIMR));
    147 	DPRINTF((TEXT("NITR:   ")));	// trigger
    148 	bitdisp(_reg_read_2(HD64465_NITR));
    149 
    150 #if 0 // monitoring HD64465 interrupt request.
    151 	suspendIntr();
    152 	while (1)
    153 		bitdisp(_reg_read_2(HD64465_NIRR));
    154 	/* NOTREACHED */
    155 #endif
    156 }
    157 
    158 void
    159 SH4dev::mq100_dump()
    160 {
    161 	uint32_t a, e;
    162 	int i;
    163 
    164 	// This is HPW650PA test. 640 * 480 linebytes 1280.
    165 	DPRINTF((TEXT("<<<MQ100/HD64464>>>\n")));
    166 	a = MQ100_FB_BASE + 0x4b000;
    167 	e = a + 640 * 480 * sizeof(uint16_t);
    168 	while (a < e) {
    169 		for (i = 0; i < 640; i++, a += sizeof(uint16_t))
    170 			_reg_write_2(a, ~_reg_read_2(a) & 0xffff);
    171 	}
    172 }
    173