1 /* $NetBSD: uda1341.h,v 1.3 2008/04/28 20:23:21 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Ichiro FUKUHARA (ichiro (at) ichiro.org). 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Philips UDA1341 L3 type 33 */ 34 35 /* 36 * Microcontroller L3-interface timing (MIN) 37 * expressed in micro-second 38 */ 39 #define L3_DATA_SETUP 1 /* 190 nsec */ 40 #define L3_DATA_HOLD 1 /* 30 nsec */ 41 #define L3_MODE_SETUP 1 /* 190 nsec */ 42 #define L3_MODE_HOLD 1 /* 190 nsec */ 43 #define L3_CLK_HIGH 1 /* 250 nsec */ 44 #define L3_CLK_LOW 1 /* 250 nsec */ 45 #define L3_HALT 1 /* 190 nsec */ 46 47 /* 48 * Philips UDA1341 L3 address and command types 49 */ 50 #define L3_ADDRESS_COM 5 51 #define L3_ADDRESS_DATA0 0 52 #define L3_ADDRESS_DATA1 1 53 #define L3_ADDRESS_STATUS 2 54 55 /* 56 * Philips UDA1341 Status control 57 */ 58 #define STATUS0_RST (1<<0) /* UDA1341 Reset */ 59 #define STATUS0_SC_512 (0<<4) /* System clock freq. 60 512fs */ 61 #define STATUS0_SC_384 (1<<4) /* 384fs */ 62 #define STATUS0_SC_256 (2<<4) /* 256fs */ 63 #define STATUS0_IF_I2S (0<<1) /* Data Input format 64 I2C */ 65 #define STATUS0_IF_LSB16 (1<<1) /* LSB 16 bits */ 66 #define STATUS0_IF_LSB18 (2<<1) /* LSB 18 bits */ 67 #define STATUS0_IF_LSB20 (3<<1) /* LSB 20 bits */ 68 #define STATUS0_IF_MSB (4<<1) /* MSB */ 69 #define STATUS0_IF_MSB16 (5<<1) /* LSB 16 bits and MSB-output */ 70 #define STATUS0_IF_MSB18 (6<<1) /* LSB 18 bits and MSB-output */ 71 #define STATUS0_IF_MSB20 (7<<1) /* LSB 20 bits and MSB-output */ 72 #define STATUS0_DC (1<<0) /* UDA1341 DC-filter ON */ 73 74 #define STATUS1_OGS (1<<6) /* UDA1341 DAC Gain switch */ 75 #define STATUS1_IGS (1<<5) /* UDA1341 ADC Gain switch */ 76 #define STATUS1_PAD (1<<4) /* Polarity of ADC is inverting */ 77 #define STATUS1_PDA (1<<3) /* Polarity of DAC is inverting */ 78 #define STATUS1_DS (1<<2) /* double speed playback */ 79 #define STATUS1_PC_OFF (0<<0) /* ADC:off DAC:off */ 80 #define STATUS1_PC_DAC (1<<0) /* ADC:off DAC:on */ 81 #define STATUS1_PC_ADC (2<<0) /* ADC:on DAC:off */ 82 #define STATUS1_PC_ON (3<<0) /* ADC:on DAC:on */ 83 84 /* 85 * Philips UDA1341 DATA0 control 86 */ 87 /* Data0 direct programming registers (8 bits) */ 88 #define DATA0_VC(val) (63 - (((val)+1) * 63) / 100) 89 /* Volume control val=(0<->100) */ 90 #define DATA0_COMMON (0<<6) /* DATA0_0 common bits(6-7) */ 91 92 #define DATA1_BB(val) (((((val)+1) * 15) / 100) << 3) 93 /* Bass Boost control val=(0<->100) */ 94 #define DATA1_TR(val) ((((val)+1) * 3) / 100) 95 /* Treble control val=(0<->100) */ 96 #define DATA1_COMMON (1<<6) /* DATA0_1 common bits(6-7) */ 97 98 #define DATA2_MODE_FLAT (0<<0) /* Mode filter is flat */ 99 #define DATA2_MODE_MIN (2<<0) /* Mode filter is minimum */ 100 #define DATA2_MODE_MAX (3<<0) /* Mode filter is maximum */ 101 #define DATA2_MUTE (1<<2) /* Mute on */ 102 #define DATA2_PP (1<<5) /* Peak Detection */ 103 #define DATA2_COMMON (2<<6) /* DATA0_2 common bits(6-7) */ 104 105 /* Data0 extended programming registers (16 bits) */ 106 #define EXT_ADDR_COMMON (3<<6) /* Extended Address Common bits */ 107 # define EXT_ADDR_E0 0 /* Extended Address of E0 */ 108 # define EXT_ADDR_E1 1 /* Extended Address of E1 */ 109 # define EXT_ADDR_E2 2 /* Extended Address of E2 */ 110 # define EXT_ADDR_E3 4 /* Extended Address of E3 */ 111 # define EXT_ADDR_E4 5 /* Extended Address of E4 */ 112 # define EXT_ADDR_E5 6 /* Extended Address of E5 */ 113 114 #define EXT_DATA_COMMN (7<<5) /* Extended Data Common bits */ 115 #define DATA_E0_MA(val) ((((val) + 1) * 31) / 100) 116 /* mixer gain control val=(0<->100) */ 117 #define DATA_E1_MB(val) ((((val) + 1) * 31) / 100) 118 /* mixer gain control val=(0<->100) */ 119 #define DATA_E2_MS(val) (((((val) + 1) * 6) / 100) << 3) 120 /* MIC sensitivity control val=(0<->100) */ 121 #define DATA_E2_MM0 0 /* Double differential mode */ 122 #define DATA_E2_MM1 1 /* input channel 1 select */ 123 #define DATA_E2_MM2 2 /* input channel 2 select */ 124 #define DATA_E2_MM3 3 /* digital mixer mode */ 125 126 #define DATA_E3_AG (1<<4) /* AGC control ON */ 127 #define DATA_E3_IG_L(val) (((val * 127) / 100) & 3) 128 /* Input AMP-Gain control (low 2 bits) */ 129 #define DATA_E4_IG_H(val) (((val * 127) / 100) >> 2) 130 /* Input AMP-Gain control (high 5 bits) */ 131 #define DATA_E5_AL(val) (((val + 1) * 3) / 100) 132 /* AGC output level val=(0<->100) */ 133 /* end of uda1341.h */ 134
Indexes created Sun Sep 21 15:09:59 GMT 2025