1 1.5 martin /* $NetBSD: it8368reg.h,v 1.5 2008/04/28 20:23:21 martin Exp $ */ 2 1.1 uch 3 1.4 uch /*- 4 1.4 uch * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.4 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.4 uch * by UCHIYAMA Yasushi. 9 1.4 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.4 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.4 uch * notice, this list of conditions and the following disclaimer in the 17 1.4 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.4 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.4 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.4 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.4 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.4 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.4 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.4 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.4 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.4 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.4 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.4 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.1 uch 32 1.1 uch /* 33 1.1 uch * ITE IT8368E PCMCIA/GPIO Buffer Chip 34 1.1 uch * http://www.ite.com/tw/mobile/it8368v07.pdf 35 1.1 uch */ 36 1.1 uch #define IT8368_GPIODATAOUT_REG 0x00 37 1.1 uch #define IT8368_MFIODATAOUT_REG 0x02 38 1.1 uch #define IT8368_GPIODIR_REG 0x04 39 1.1 uch #define IT8368_MFIODIR_REG 0x06 40 1.1 uch #define IT8368_MFIOSEL_REG 0x0a 41 1.1 uch #define IT8368_GPIODATAIN_REG 0x0c 42 1.1 uch #define IT8368_MFIODATAIN_REG 0x0e 43 1.1 uch #define IT8368_GPIOPOSINTEN_REG 0x10 44 1.1 uch #define IT8368_MFIOPOSINTEN_REG 0x12 45 1.1 uch #define IT8368_GPIONEGINTEN_REG 0x14 46 1.1 uch #define IT8368_MFIONEGINTEN_REG 0x16 47 1.1 uch #define IT8368_GPIOPOSINTSTAT_REG 0x18 48 1.1 uch #define IT8368_MFIOPOSINTSTAT_REG 0x1a 49 1.1 uch #define IT8368_GPIONEGINTSTAT_REG 0x1c 50 1.1 uch #define IT8368_MFIONEGINTSTAT_REG 0x1e 51 1.1 uch #define IT8368_CTRL_REG 0x20 52 1.2 uch 53 1.3 uch #define IT8368_GPIO_MAX 12 54 1.3 uch #define IT8368_MFIO_MAX 10 55 1.1 uch 56 1.1 uch #define IT8368_GPIODATAOUT_MASK 0x1fff 57 1.1 uch #define IT8368_MFIODATAOUT_MASK 0x07ff 58 1.1 uch #define IT8368_GPIODIR_MASK 0x1fff 59 1.1 uch #define IT8368_MFIODIR_MASK 0x07ff 60 1.1 uch 61 1.1 uch #define IT8368_MFIOSEL_VGAEN 0x0800 62 1.1 uch #define IT8368_MFIOSEL_MASK 0x07ff 63 1.1 uch #define IT8368_GPIODATAIN_MASK 0x1fff 64 1.1 uch #define IT8368_MFIODATAIN_MASK 0x07ff 65 1.1 uch #define IT8368_GPIOPOSINTEN_MASK 0x1fff 66 1.1 uch #define IT8368_MFIOPOSINTEN_MASK 0x07ff 67 1.1 uch #define IT8368_GPIONEGINTEN_MASK 0x1fff 68 1.1 uch #define IT8368_MFIONEGINTEN_MASK 0x07ff 69 1.1 uch #define IT8368_GPIOPOSINTSTAT_MASK 0x1fff 70 1.1 uch #define IT8368_MFIOPOSINTSTAT_MASK 0x07ff 71 1.1 uch #define IT8368_GPIONEGINTSTAT_MASK 0x1fff 72 1.1 uch #define IT8368_MFIONEGINTSTAT_MASK 0x07ff 73 1.1 uch 74 1.1 uch 75 1.1 uch #define IT8368_CTRL_FIXATTRIO 0x8000 76 1.1 uch #define IT8368_FIXATTR_OFFSET 0x02000000 77 1.1 uch #define IT8368_FIXIO_OFFSET 0x0 78 1.1 uch #define IT8368_FIXIOATTR_SIZE 0x02000000 79 1.1 uch 80 1.1 uch #define IT8368_CTRL_ADDRSEL 0x0010 81 1.1 uch #define IT8368_CTRL_BYTESWAP 0x0008 82 1.1 uch #define IT8368_CTRL_CARDEN 0x0004 83 1.1 uch #define IT8368_CTRL_GLOBALEN 0x0002 84 1.1 uch #define IT8368_CTRL_INTTRIEN 0x0001 85 1.1 uch 86 1.1 uch #define IT8368_PIN_CRDSW 0x1000 87 1.1 uch #define IT8368_PIN_CRDDET2 0x0800 88 1.1 uch #define IT8368_PIN_CRDDET1 0x0400 89 1.1 uch #define IT8368_PIN_CRDSENSE2 0x0200 90 1.1 uch #define IT8368_PIN_CRDSENSE1 0x0100 91 1.1 uch #define IT8368_PIN_CRDVCCON1 0x0080 92 1.1 uch #define IT8368_PIN_CRDVCCON0 0x0040 93 1.1 uch #define IT8368_PIN_CRDVPPON1 0x0020 94 1.1 uch #define IT8368_PIN_CRDVPPON0 0x0010 95 1.1 uch #define IT8368_PIN_BCRDWP 0x0008 96 1.1 uch #define IT8368_PIN_BCRDRDY 0x0004 97 1.1 uch #define IT8368_PIN_BCRBVD2 0x0002 98 1.1 uch #define IT8368_PIN_BCRDRST 0x0001 99 1.1 uch 100 1.1 uch #define IT8368_PIN_CRDVCCMASK 0x00c0 101 1.1 uch #define IT8368_PIN_CRDVPPMASK 0x0030 102 1.1 uch #define IT8368_PIN_CRDVCC_0V 0x0000 103 1.1 uch #define IT8368_PIN_CRDVCC_3V IT8368_PIN_CRDVCCON0 104 1.1 uch #define IT8368_PIN_CRDVCC_5V IT8368_PIN_CRDVCCON1 105 1.1 uch #define IT8368_PIN_CRDVPP_0V 0x0000 106 1.1 uch #define IT8368_PIN_CRDVPP_CRDVCC IT8368_PIN_CRDVPPON0 107 1.1 uch #define IT8368_PIN_CRDVCC_12V IT8368_PIN_CRDVPPON1 108 1.3 uch #define IT8368_PIN_CRDVCC_HIZ (IT8368_PIN_CRDVPPON0 | \ 109 1.3 uch IT8368_PIN_CRDVPPON1) 110
Indexes created Tue Sep 23 02:09:52 GMT 2025