1 /* $NetBSD: it8368reg.h,v 1.5 2008/04/28 20:23:21 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * ITE IT8368E PCMCIA/GPIO Buffer Chip 34 * http://www.ite.com/tw/mobile/it8368v07.pdf 35 */ 36 #define IT8368_GPIODATAOUT_REG 0x00 37 #define IT8368_MFIODATAOUT_REG 0x02 38 #define IT8368_GPIODIR_REG 0x04 39 #define IT8368_MFIODIR_REG 0x06 40 #define IT8368_MFIOSEL_REG 0x0a 41 #define IT8368_GPIODATAIN_REG 0x0c 42 #define IT8368_MFIODATAIN_REG 0x0e 43 #define IT8368_GPIOPOSINTEN_REG 0x10 44 #define IT8368_MFIOPOSINTEN_REG 0x12 45 #define IT8368_GPIONEGINTEN_REG 0x14 46 #define IT8368_MFIONEGINTEN_REG 0x16 47 #define IT8368_GPIOPOSINTSTAT_REG 0x18 48 #define IT8368_MFIOPOSINTSTAT_REG 0x1a 49 #define IT8368_GPIONEGINTSTAT_REG 0x1c 50 #define IT8368_MFIONEGINTSTAT_REG 0x1e 51 #define IT8368_CTRL_REG 0x20 52 53 #define IT8368_GPIO_MAX 12 54 #define IT8368_MFIO_MAX 10 55 56 #define IT8368_GPIODATAOUT_MASK 0x1fff 57 #define IT8368_MFIODATAOUT_MASK 0x07ff 58 #define IT8368_GPIODIR_MASK 0x1fff 59 #define IT8368_MFIODIR_MASK 0x07ff 60 61 #define IT8368_MFIOSEL_VGAEN 0x0800 62 #define IT8368_MFIOSEL_MASK 0x07ff 63 #define IT8368_GPIODATAIN_MASK 0x1fff 64 #define IT8368_MFIODATAIN_MASK 0x07ff 65 #define IT8368_GPIOPOSINTEN_MASK 0x1fff 66 #define IT8368_MFIOPOSINTEN_MASK 0x07ff 67 #define IT8368_GPIONEGINTEN_MASK 0x1fff 68 #define IT8368_MFIONEGINTEN_MASK 0x07ff 69 #define IT8368_GPIOPOSINTSTAT_MASK 0x1fff 70 #define IT8368_MFIOPOSINTSTAT_MASK 0x07ff 71 #define IT8368_GPIONEGINTSTAT_MASK 0x1fff 72 #define IT8368_MFIONEGINTSTAT_MASK 0x07ff 73 74 75 #define IT8368_CTRL_FIXATTRIO 0x8000 76 #define IT8368_FIXATTR_OFFSET 0x02000000 77 #define IT8368_FIXIO_OFFSET 0x0 78 #define IT8368_FIXIOATTR_SIZE 0x02000000 79 80 #define IT8368_CTRL_ADDRSEL 0x0010 81 #define IT8368_CTRL_BYTESWAP 0x0008 82 #define IT8368_CTRL_CARDEN 0x0004 83 #define IT8368_CTRL_GLOBALEN 0x0002 84 #define IT8368_CTRL_INTTRIEN 0x0001 85 86 #define IT8368_PIN_CRDSW 0x1000 87 #define IT8368_PIN_CRDDET2 0x0800 88 #define IT8368_PIN_CRDDET1 0x0400 89 #define IT8368_PIN_CRDSENSE2 0x0200 90 #define IT8368_PIN_CRDSENSE1 0x0100 91 #define IT8368_PIN_CRDVCCON1 0x0080 92 #define IT8368_PIN_CRDVCCON0 0x0040 93 #define IT8368_PIN_CRDVPPON1 0x0020 94 #define IT8368_PIN_CRDVPPON0 0x0010 95 #define IT8368_PIN_BCRDWP 0x0008 96 #define IT8368_PIN_BCRDRDY 0x0004 97 #define IT8368_PIN_BCRBVD2 0x0002 98 #define IT8368_PIN_BCRDRST 0x0001 99 100 #define IT8368_PIN_CRDVCCMASK 0x00c0 101 #define IT8368_PIN_CRDVPPMASK 0x0030 102 #define IT8368_PIN_CRDVCC_0V 0x0000 103 #define IT8368_PIN_CRDVCC_3V IT8368_PIN_CRDVCCON0 104 #define IT8368_PIN_CRDVCC_5V IT8368_PIN_CRDVCCON1 105 #define IT8368_PIN_CRDVPP_0V 0x0000 106 #define IT8368_PIN_CRDVPP_CRDVCC IT8368_PIN_CRDVPPON0 107 #define IT8368_PIN_CRDVCC_12V IT8368_PIN_CRDVPPON1 108 #define IT8368_PIN_CRDVCC_HIZ (IT8368_PIN_CRDVPPON0 | \ 109 IT8368_PIN_CRDVPPON1) 110
Indexes created Sat Sep 20 22:09:52 GMT 2025