it8368reg.h revision 1.3
1 /* $NetBSD: it8368reg.h,v 1.3 2000/03/12 15:35:29 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000 by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* 30 * ITE IT8368E PCMCIA/GPIO Buffer Chip 31 * http://www.ite.com/tw/mobile/it8368v07.pdf 32 */ 33 #define IT8368_GPIODATAOUT_REG 0x00 34 #define IT8368_MFIODATAOUT_REG 0x02 35 #define IT8368_GPIODIR_REG 0x04 36 #define IT8368_MFIODIR_REG 0x06 37 #define IT8368_MFIOSEL_REG 0x0a 38 #define IT8368_GPIODATAIN_REG 0x0c 39 #define IT8368_MFIODATAIN_REG 0x0e 40 #define IT8368_GPIOPOSINTEN_REG 0x10 41 #define IT8368_MFIOPOSINTEN_REG 0x12 42 #define IT8368_GPIONEGINTEN_REG 0x14 43 #define IT8368_MFIONEGINTEN_REG 0x16 44 #define IT8368_GPIOPOSINTSTAT_REG 0x18 45 #define IT8368_MFIOPOSINTSTAT_REG 0x1a 46 #define IT8368_GPIONEGINTSTAT_REG 0x1c 47 #define IT8368_MFIONEGINTSTAT_REG 0x1e 48 #define IT8368_CTRL_REG 0x20 49 50 #define IT8368_GPIO_MAX 12 51 #define IT8368_MFIO_MAX 10 52 53 #define IT8368_GPIODATAOUT_MASK 0x1fff 54 #define IT8368_MFIODATAOUT_MASK 0x07ff 55 #define IT8368_GPIODIR_MASK 0x1fff 56 #define IT8368_MFIODIR_MASK 0x07ff 57 58 #define IT8368_MFIOSEL_VGAEN 0x0800 59 #define IT8368_MFIOSEL_MASK 0x07ff 60 #define IT8368_GPIODATAIN_MASK 0x1fff 61 #define IT8368_MFIODATAIN_MASK 0x07ff 62 #define IT8368_GPIOPOSINTEN_MASK 0x1fff 63 #define IT8368_MFIOPOSINTEN_MASK 0x07ff 64 #define IT8368_GPIONEGINTEN_MASK 0x1fff 65 #define IT8368_MFIONEGINTEN_MASK 0x07ff 66 #define IT8368_GPIOPOSINTSTAT_MASK 0x1fff 67 #define IT8368_MFIOPOSINTSTAT_MASK 0x07ff 68 #define IT8368_GPIONEGINTSTAT_MASK 0x1fff 69 #define IT8368_MFIONEGINTSTAT_MASK 0x07ff 70 71 72 #define IT8368_CTRL_FIXATTRIO 0x8000 73 #define IT8368_FIXATTR_OFFSET 0x02000000 74 #define IT8368_FIXIO_OFFSET 0x0 75 #define IT8368_FIXIOATTR_SIZE 0x02000000 76 77 #define IT8368_CTRL_ADDRSEL 0x0010 78 #define IT8368_CTRL_BYTESWAP 0x0008 79 #define IT8368_CTRL_CARDEN 0x0004 80 #define IT8368_CTRL_GLOBALEN 0x0002 81 #define IT8368_CTRL_INTTRIEN 0x0001 82 83 #define IT8368_PIN_CRDSW 0x1000 84 #define IT8368_PIN_CRDDET2 0x0800 85 #define IT8368_PIN_CRDDET1 0x0400 86 #define IT8368_PIN_CRDSENSE2 0x0200 87 #define IT8368_PIN_CRDSENSE1 0x0100 88 #define IT8368_PIN_CRDVCCON1 0x0080 89 #define IT8368_PIN_CRDVCCON0 0x0040 90 #define IT8368_PIN_CRDVPPON1 0x0020 91 #define IT8368_PIN_CRDVPPON0 0x0010 92 #define IT8368_PIN_BCRDWP 0x0008 93 #define IT8368_PIN_BCRDRDY 0x0004 94 #define IT8368_PIN_BCRBVD2 0x0002 95 #define IT8368_PIN_BCRDRST 0x0001 96 97 #define IT8368_PIN_CRDVCCMASK 0x00c0 98 #define IT8368_PIN_CRDVPPMASK 0x0030 99 #define IT8368_PIN_CRDVCC_0V 0x0000 100 #define IT8368_PIN_CRDVCC_3V IT8368_PIN_CRDVCCON0 101 #define IT8368_PIN_CRDVCC_5V IT8368_PIN_CRDVCCON1 102 #define IT8368_PIN_CRDVPP_0V 0x0000 103 #define IT8368_PIN_CRDVPP_CRDVCC IT8368_PIN_CRDVPPON0 104 #define IT8368_PIN_CRDVCC_12V IT8368_PIN_CRDVPPON1 105 #define IT8368_PIN_CRDVCC_HIZ (IT8368_PIN_CRDVPPON0 | \ 106 IT8368_PIN_CRDVPPON1) 107
Indexes created Sun Sep 28 12:09:53 GMT 2025