1 1.4 martin /* $NetBSD: plumpowerreg.h,v 1.4 2008/04/28 20:23:21 martin Exp $ */ 2 1.1 uch 3 1.3 uch /*- 4 1.3 uch * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.3 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.3 uch * by UCHIYAMA Yasushi. 9 1.3 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.3 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.3 uch * notice, this list of conditions and the following disclaimer in the 17 1.3 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.3 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.3 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.3 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.3 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.3 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.3 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.3 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.3 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.3 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.3 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.3 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.1 uch 32 1.1 uch /* 33 1.1 uch * POWER CONTROLLER 34 1.1 uch */ 35 1.1 uch #define PLUM_POWER_REGBASE 0x7000 36 1.1 uch #define PLUM_POWER_REGSIZE 0x1000 37 1.1 uch 38 1.1 uch /* power control register */ 39 1.1 uch #define PLUM_POWER_PWRCONT_REG 0x000 40 1.1 uch 41 1.1 uch #define PLUM_POWER_PWRCONT_USBEN 0x00000400 42 1.1 uch #define PLUM_POWER_PWRCONT_IO5OE 0x00000200 43 1.1 uch #define PLUM_POWER_PWRCONT_LCDOE 0x00000100 44 1.3 uch /* EXTPW[0:2] Platform dependent control signal */ 45 1.1 uch #define PLUM_POWER_PWRCONT_EXTPW2 0x00000040 46 1.1 uch #define PLUM_POWER_PWRCONT_EXTPW1 0x00000020 47 1.1 uch #define PLUM_POWER_PWRCONT_EXTPW0 0x00000010 48 1.1 uch #define PLUM_POWER_PWRCONT_IO5PWR 0x00000008 49 1.1 uch #define PLUM_POWER_PWRCONT_BKLIGHT 0x00000004 50 1.1 uch #define PLUM_POWER_PWRCONT_LCDPWR 0x00000002 51 1.1 uch #define PLUM_POWER_PWRCONT_LCDDSP 0x00000001 52 1.1 uch 53 1.1 uch /* clock control register */ 54 1.1 uch #define PLUM_POWER_CLKCONT_REG 0x004 55 1.1 uch 56 1.1 uch #define PLUM_POWER_CLKCONT_USBCLK2 0x00000020 57 1.1 uch #define PLUM_POWER_CLKCONT_USBCLK1 0x00000010 58 1.1 uch #define PLUM_POWER_CLKCONT_IO5CLK 0x00000008 59 1.1 uch #define PLUM_POWER_CLKCONT_SMCLK 0x00000004 60 1.1 uch #define PLUM_POWER_CLKCONT_PCCCLK2 0x00000002 61 1.1 uch #define PLUM_POWER_CLKCONT_PCCCLK1 0x00000001 62 1.1 uch 63 1.1 uch /* mask rom control register */ 64 1.1 uch #define PLUM_POWER_MROMCNT_REG 0x008 65 1.1 uch 66 1.1 uch #define PLUM_POWER_MROMCNT_MROMSL1 0x00000004 67 1.1 uch #define PLUM_POWER_MROMCNT_MROMSL0 0x00000002 68 1.1 uch #define PLUM_POWER_MROMCNT_MRMAEN 0x00000001 69 1.1 uch #define PLUM_POWER_MROMCNT_MROM_8MB 0x0 70 1.1 uch #define PLUM_POWER_MROMCNT_MROM_4MB 0x1 71 1.1 uch #define PLUM_POWER_MROMCNT_MROM_16MB 0x2 72 1.1 uch 73 1.1 uch /* input signal enable register (MCS access) */ 74 1.1 uch #define PLUM_POWER_INPENA_REG 0x00c 75 1.1 uch #define PLUM_POWER_INPENA 0x00000001 76 1.1 uch 77 1.1 uch /* reset control register (I/O bus)*/ 78 1.1 uch #define PLUM_POWER_RESETC_REG 0x010 79 1.2 uch /* Active High control */ 80 1.1 uch #define PLUM_POWER_RESETC_IO5CL1 0x00000002 81 1.2 uch /* Active Low control */ 82 1.1 uch #define PLUM_POWER_RESETC_IO5CL0 0x00000001 83 1.1 uch 84 1.1 uch #define PLUM_POWER_TESTMD_REG 0x100 85
Indexes created Tue Sep 23 01:09:51 GMT 2025