1 /* $NetBSD: plumpowerreg.h,v 1.4 2008/04/28 20:23:21 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * POWER CONTROLLER 34 */ 35 #define PLUM_POWER_REGBASE 0x7000 36 #define PLUM_POWER_REGSIZE 0x1000 37 38 /* power control register */ 39 #define PLUM_POWER_PWRCONT_REG 0x000 40 41 #define PLUM_POWER_PWRCONT_USBEN 0x00000400 42 #define PLUM_POWER_PWRCONT_IO5OE 0x00000200 43 #define PLUM_POWER_PWRCONT_LCDOE 0x00000100 44 /* EXTPW[0:2] Platform dependent control signal */ 45 #define PLUM_POWER_PWRCONT_EXTPW2 0x00000040 46 #define PLUM_POWER_PWRCONT_EXTPW1 0x00000020 47 #define PLUM_POWER_PWRCONT_EXTPW0 0x00000010 48 #define PLUM_POWER_PWRCONT_IO5PWR 0x00000008 49 #define PLUM_POWER_PWRCONT_BKLIGHT 0x00000004 50 #define PLUM_POWER_PWRCONT_LCDPWR 0x00000002 51 #define PLUM_POWER_PWRCONT_LCDDSP 0x00000001 52 53 /* clock control register */ 54 #define PLUM_POWER_CLKCONT_REG 0x004 55 56 #define PLUM_POWER_CLKCONT_USBCLK2 0x00000020 57 #define PLUM_POWER_CLKCONT_USBCLK1 0x00000010 58 #define PLUM_POWER_CLKCONT_IO5CLK 0x00000008 59 #define PLUM_POWER_CLKCONT_SMCLK 0x00000004 60 #define PLUM_POWER_CLKCONT_PCCCLK2 0x00000002 61 #define PLUM_POWER_CLKCONT_PCCCLK1 0x00000001 62 63 /* mask rom control register */ 64 #define PLUM_POWER_MROMCNT_REG 0x008 65 66 #define PLUM_POWER_MROMCNT_MROMSL1 0x00000004 67 #define PLUM_POWER_MROMCNT_MROMSL0 0x00000002 68 #define PLUM_POWER_MROMCNT_MRMAEN 0x00000001 69 #define PLUM_POWER_MROMCNT_MROM_8MB 0x0 70 #define PLUM_POWER_MROMCNT_MROM_4MB 0x1 71 #define PLUM_POWER_MROMCNT_MROM_16MB 0x2 72 73 /* input signal enable register (MCS access) */ 74 #define PLUM_POWER_INPENA_REG 0x00c 75 #define PLUM_POWER_INPENA 0x00000001 76 77 /* reset control register (I/O bus)*/ 78 #define PLUM_POWER_RESETC_REG 0x010 79 /* Active High control */ 80 #define PLUM_POWER_RESETC_IO5CL1 0x00000002 81 /* Active Low control */ 82 #define PLUM_POWER_RESETC_IO5CL0 0x00000001 83 84 #define PLUM_POWER_TESTMD_REG 0x100 85
Indexes created Sat Sep 20 22:09:52 GMT 2025