plumpowerreg.h revision 1.2
1 /* $NetBSD: plumpowerreg.h,v 1.2 1999/12/07 17:21:45 uch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, by UCHIYAMA Yasushi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the developer may NOT be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 /* 30 * POWER CONTROLLER 31 */ 32 #define PLUM_POWER_REGBASE 0x7000 33 #define PLUM_POWER_REGSIZE 0x1000 34 35 /* power control register */ 36 #define PLUM_POWER_PWRCONT_REG 0x000 37 38 #define PLUM_POWER_PWRCONT_USBEN 0x00000400 39 #define PLUM_POWER_PWRCONT_IO5OE 0x00000200 40 #define PLUM_POWER_PWRCONT_LCDOE 0x00000100 41 /* Enable signal of oscillator for the VRAM control */ 42 #define PLUM_POWER_PWRCONT_EXTPW2 0x00000040 43 /* Enable signal of the oscillator for LCD module */ 44 #define PLUM_POWER_PWRCONT_EXTPW1 0x00000020 45 /* FET Switch that gates power line for RAMDAC */ 46 #define PLUM_POWER_PWRCONT_EXTPW0 0x00000010 47 #define PLUM_POWER_PWRCONT_IO5PWR 0x00000008 48 #define PLUM_POWER_PWRCONT_BKLIGHT 0x00000004 49 #define PLUM_POWER_PWRCONT_LCDPWR 0x00000002 50 #define PLUM_POWER_PWRCONT_LCDDSP 0x00000001 51 52 /* clock control register */ 53 #define PLUM_POWER_CLKCONT_REG 0x004 54 55 #define PLUM_POWER_CLKCONT_USBCLK2 0x00000020 56 #define PLUM_POWER_CLKCONT_USBCLK1 0x00000010 57 #define PLUM_POWER_CLKCONT_IO5CLK 0x00000008 58 #define PLUM_POWER_CLKCONT_SMCLK 0x00000004 59 #define PLUM_POWER_CLKCONT_PCCCLK2 0x00000002 60 #define PLUM_POWER_CLKCONT_PCCCLK1 0x00000001 61 62 /* mask rom control register */ 63 #define PLUM_POWER_MROMCNT_REG 0x008 64 65 #define PLUM_POWER_MROMCNT_MROMSL1 0x00000004 66 #define PLUM_POWER_MROMCNT_MROMSL0 0x00000002 67 #define PLUM_POWER_MROMCNT_MRMAEN 0x00000001 68 #define PLUM_POWER_MROMCNT_MROM_8MB 0x0 69 #define PLUM_POWER_MROMCNT_MROM_4MB 0x1 70 #define PLUM_POWER_MROMCNT_MROM_16MB 0x2 71 72 /* input signal enable register (MCS access) */ 73 #define PLUM_POWER_INPENA_REG 0x00c 74 #define PLUM_POWER_INPENA 0x00000001 75 76 /* reset control register (I/O bus)*/ 77 #define PLUM_POWER_RESETC_REG 0x010 78 /* Active High control */ 79 #define PLUM_POWER_RESETC_IO5CL1 0x00000002 80 /* Active Low control */ 81 #define PLUM_POWER_RESETC_IO5CL0 0x00000001 82 83 #define PLUM_POWER_TESTMD_REG 0x100 84
Indexes created Mon Sep 29 03:10:08 GMT 2025