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plumpowerreg.h revision 1.3
      1 /*	$NetBSD: plumpowerreg.h,v 1.3 2000/10/04 13:53:55 uch Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by UCHIYAMA Yasushi.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 /*
     40  * POWER CONTROLLER
     41  */
     42 #define	PLUM_POWER_REGBASE		0x7000
     43 #define	PLUM_POWER_REGSIZE		0x1000
     44 
     45 /* power control register */
     46 #define PLUM_POWER_PWRCONT_REG		0x000
     47 
     48 #define PLUM_POWER_PWRCONT_USBEN	0x00000400
     49 #define PLUM_POWER_PWRCONT_IO5OE	0x00000200
     50 #define PLUM_POWER_PWRCONT_LCDOE	0x00000100
     51 /* EXTPW[0:2] Platform dependent control signal */
     52 #define PLUM_POWER_PWRCONT_EXTPW2	0x00000040
     53 #define PLUM_POWER_PWRCONT_EXTPW1	0x00000020
     54 #define PLUM_POWER_PWRCONT_EXTPW0	0x00000010
     55 #define PLUM_POWER_PWRCONT_IO5PWR	0x00000008
     56 #define PLUM_POWER_PWRCONT_BKLIGHT	0x00000004
     57 #define PLUM_POWER_PWRCONT_LCDPWR	0x00000002
     58 #define PLUM_POWER_PWRCONT_LCDDSP	0x00000001
     59 
     60 /* clock control register */
     61 #define PLUM_POWER_CLKCONT_REG		0x004
     62 
     63 #define	PLUM_POWER_CLKCONT_USBCLK2	0x00000020
     64 #define	PLUM_POWER_CLKCONT_USBCLK1	0x00000010
     65 #define	PLUM_POWER_CLKCONT_IO5CLK	0x00000008
     66 #define	PLUM_POWER_CLKCONT_SMCLK	0x00000004
     67 #define	PLUM_POWER_CLKCONT_PCCCLK2	0x00000002
     68 #define	PLUM_POWER_CLKCONT_PCCCLK1	0x00000001
     69 
     70 /* mask rom control register */
     71 #define PLUM_POWER_MROMCNT_REG		0x008
     72 
     73 #define PLUM_POWER_MROMCNT_MROMSL1	0x00000004
     74 #define PLUM_POWER_MROMCNT_MROMSL0	0x00000002
     75 #define PLUM_POWER_MROMCNT_MRMAEN	0x00000001
     76 #define PLUM_POWER_MROMCNT_MROM_8MB	0x0
     77 #define PLUM_POWER_MROMCNT_MROM_4MB	0x1
     78 #define PLUM_POWER_MROMCNT_MROM_16MB	0x2
     79 
     80 /* input signal enable register (MCS access) */
     81 #define PLUM_POWER_INPENA_REG		0x00c
     82 #define PLUM_POWER_INPENA		0x00000001
     83 
     84 /* reset control register (I/O bus)*/
     85 #define PLUM_POWER_RESETC_REG		0x010
     86 /* Active High control */
     87 #define PLUM_POWER_RESETC_IO5CL1	0x00000002
     88 /* Active Low control */
     89 #define PLUM_POWER_RESETC_IO5CL0	0x00000001
     90 
     91 #define PLUM_POWER_TESTMD_REG		0x100
     92