1 /* $NetBSD: vr4181aiureg.h,v 1.2 2008/04/28 20:23:22 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Naoto Shimazaki of YOKOGAWA Electric Corporation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * VR4181 AIU (Audio Interface Unit) Registers definitions. 34 */ 35 36 #define VR4181AIU_DCU1_BASE 0x0a000020 37 #define VR4181AIU_DCU1_SIZE 0x28 38 #define VR4181AIU_DCU2_BASE 0x0a000650 39 #define VR4181AIU_DCU2_SIZE 0x18 40 #define VR4181AIU_AIU_BASE 0x0b000160 41 #define VR4181AIU_AIU_SIZE 0x20 42 43 44 #define VR4181AIU_SDMADAT_REG_W 0x00 /* speaker DMA data (10bit) */ 45 46 #define VR4181AIU_MDMADAT_REG_W 0x02 /* microphone DMA data (10bit) */ 47 48 #define VR4181AIU_DAVREF_SETUP_REG_W 0x004 /* D/A Vref setup */ 49 50 #define VR4181AIU_SODATA_REG_W 0x06 /* speaker output data (10bit) */ 51 52 #define VR4181AIU_SCNT_REG_W 0x08 /* speaker control */ 53 #define VR4181AIU_DAENAIU 0x8000 /* D/A enable */ 54 #define VR4181AIU_SSTATE 0x0008 /* speaker status */ 55 #define VR4181AIU_SSTOPEN 0x0002 /* speaker stop end 56 (1: 1 page, 0: 2 page) */ 57 58 #define VR4181AIU_SCNVC_END 0x0e /* speaker convert rate */ 59 60 #define VR4181AIU_MIDAT_REG_W 0x10 /* microphone input data (10bit) */ 61 62 #define VR4181AIU_MCNT_REG_W 0x12 /* microphone control */ 63 #define VR4181AIU_ADENAIU 0x8000 /* A/D enable */ 64 #define VR4181AIU_MSTATE 0x0008 /* microphone status */ 65 #define VR4181AIU_MSTOPEN 0x0002 /* microphone stop end 66 (1: 1 page, 0: 2 page) */ 67 #define VR4181AIU_ADREQAIU 0x0001 /* A/D Request */ 68 69 #define VR4181AIU_DVALID_REG_W 0x18 /* data valid */ 70 #define VR4181AIU_SODATV 0x0008 /* SODATREG valid */ 71 #define VR4181AIU_SOMAV 0x0004 /* SDMADATREG valid */ 72 #define VR4181AIU_MIDATV 0x0002 /* MIDATREG valid */ 73 #define VR4181AIU_MDMAV 0x0001 /* MDMADATREG valid */ 74 75 #define VR4181AIU_SEQ_REG_W 0x1a /* sequencer */ 76 #define VR4181AIU_AIURST 0x8000 /* AIU reset */ 77 #define VR4181AIU_AIUMEN 0x0010 /* microphone enable */ 78 #define VR4181AIU_AIUSEN 0x0001 /* speaker enable */ 79 80 #define VR4181AIU_INT_REG_W 0x1c /* interrupt */ 81 #define VR4181AIU_MIDLEINTR 0x0200 /* microphone idle interrupt */ 82 #define VR4181AIU_MSTINTR 0x0100 /* microphone set interrupt */ 83 #define VR4181AIU_SIDLEINTR 0x0002 /* speaker idle interrupt */ 84 85 #define VR4181AIU_MCNVC_END 0x1e /* microphone convert rate */ 86
Indexes created Mon Sep 29 15:09:53 GMT 2025