1 /* $NetBSD: vraiureg.h,v 1.1 2002/03/23 09:02:02 hamajima Exp $ */ 2 3 /* 4 * Copyright (c) 2001 HAMAJIMA Katsuomi. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * AIU (Audio Interface Unit) Registers definitions. 30 */ 31 32 #define MDMADAT_REG_W 0x000 /* Mic DMA Data Register (10bit) */ 33 34 #define SDMADAT_REG_W 0x002 /* Speaker DMA Data Register (10bit) */ 35 36 #define SODATA_REG_W 0x006 /* Speaker Output Data Register (10bit) */ 37 38 #define SCNT_REG_W 0x008 /* Speaker Control Register */ 39 #define DAENAIU (1<<15) /* D/A Enable */ 40 #define SSTATE (1<<3) /* Speaker Status */ 41 #define SSTOPEN (1<<1) /* Speaker Stop End 42 (1: 1 page, 0: 2 page) */ 43 44 #define SCNVR_REG_W 0x00a /* Speaker Converter Rate Register */ 45 #define SPS8000 (4) /* 8k sps */ 46 #define SPS44100 (2) /* 44.1k sps */ 47 #define SPS22050 (1) /* 22.05k sps */ 48 #define SPS11025 (0) /* 11.025k sps */ 49 50 #define MIDAT_REG_W 0x010 /* Mic Input Data Register (10bit) */ 51 52 #define MCNT_REG_W 0x012 /* Mic Control Register */ 53 #define ADENAIU (1<<15) /* A/D Enable */ 54 #define MSTATE (1<<3) /* Mic Status */ 55 #define MSTOPEN (1<<1) /* Mic Stop End 56 (1: 1 page, 0: 2 page) */ 57 #define ADREQAIU (1) /* A/D Request */ 58 59 #define MCNVR_REG_W 0x014 /* Mic Converter Rate Register */ 60 /* same SCNVR_REG_W(0x00a) 61 #define SPS8000 (4) 62 #define SPS44100 (2) 63 #define SPS22050 (1) 64 #define SPS11025 (0) 65 */ 66 67 #define DVALID_REG_W 0x018 /* Data Valid Register */ 68 #define SODATV (1<<3) /* SODATREG Valid */ 69 #define SOMAV (1<<2) /* SDMADATREG Valid */ 70 #define MIDATV (1<<1) /* MIDATREG Valid */ 71 #define MDMAV (1) /* MDMADATREG Valid */ 72 73 #define SEQ_REG_W 0x01a /* Sequencer Register */ 74 #define AIURST (1<<15) /* AIU Reset */ 75 #define AIUMEN (1<<4) /* Mic Enable */ 76 #define AIUSEN (1) /* Speaker Enable */ 77 78 #define INT_REG_W 0x01c /* Interrupt Register */ 79 #define MENDINTR (1<<11) /* Mic End Interrupt */ 80 #define MINTR (1<<10) /* Mic Interrupt */ 81 #define MIDLEINTR (1<<9) /* Mic Idle Interrupt */ 82 #define MSTINTR (1<<8) /* Mic Set Interrupt */ 83 #define SENDINTR (1<<3) /* Speaker End Interrupt */ 84 #define SINTR (1<<2) /* Speaker Interrupt */ 85 #define SIDLEINTR (1<<1) /* Speaker Idle Interrupt */ 86
Indexes created Sat Sep 20 22:09:52 GMT 2025