1 1.4 martin /* $NetBSD: hd64461reg.h,v 1.4 2008/04/28 20:23:22 martin Exp $ */ 2 1.1 uch 3 1.1 uch /*- 4 1.1 uch * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.1 uch * This code is derived from software contributed to The NetBSD Foundation 8 1.1 uch * by UCHIYAMA Yasushi. 9 1.1 uch * 10 1.1 uch * Redistribution and use in source and binary forms, with or without 11 1.1 uch * modification, are permitted provided that the following conditions 12 1.1 uch * are met: 13 1.1 uch * 1. Redistributions of source code must retain the above copyright 14 1.1 uch * notice, this list of conditions and the following disclaimer. 15 1.1 uch * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 uch * notice, this list of conditions and the following disclaimer in the 17 1.1 uch * documentation and/or other materials provided with the distribution. 18 1.1 uch * 19 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.1 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.1 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.1 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.1 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.1 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.1 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.1 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.1 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.1 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.1 uch * POSSIBILITY OF SUCH DAMAGE. 30 1.1 uch */ 31 1.1 uch 32 1.3 uwe #ifndef _HPCSH_DEV_HD64461REG_H_ 33 1.3 uwe #define _HPCSH_DEV_HD64461REG_H_ 34 1.3 uwe 35 1.1 uch #define SH3_AREA4_BASE 0xb0000000 36 1.1 uch #define SH3_AREA5_BASE 0xb4000000 37 1.1 uch #define SH3_AREA6_BASE 0xb8000000 38 1.1 uch 39 1.1 uch /* HD64461 Address mapping (mapped to SH3 memory space) */ 40 1.1 uch 41 1.1 uch /* SH3 Area 4 (Register, Framebuffer) */ 42 1.1 uch #define HD64461_REGBASE SH3_AREA4_BASE 43 1.1 uch #define HD64461_REGSIZE 0x02000000 44 1.1 uch #define HD64461_FBBASE (SH3_AREA4_BASE + 0x02000000) 45 1.1 uch #define HD64461_FBSIZE 0x02000000 46 1.2 uch #define HD64461_FBPAGESIZE 0x1000 47 1.1 uch 48 1.1 uch /* SH3 Area 5 (PCC1 memory space) */ 49 1.1 uch #define HD64461_PCC1_MEMBASE SH3_AREA5_BASE 50 1.1 uch #define HD64461_PCC1_MEMSIZE 0x02000000 51 1.1 uch 52 1.1 uch /* SH3 Area 6 (PCC0 memory, I/O space*/ 53 1.1 uch #define HD64461_PCC0_MEMBASE SH3_AREA6_BASE 54 1.1 uch #define HD64461_PCC0_MEMSIZE 0x02000000 55 1.1 uch #define HD64461_PCC0_IOBASE (SH3_AREA6_BASE + 0x02000000) 56 1.1 uch #define HD64461_PCC0_IOSIZE 0x02000000 57 1.1 uch 58 1.1 uch /* 59 1.1 uch * Register mapping. 60 1.1 uch */ 61 1.1 uch #define HD64461_SYSTEM_REGBASE 0xb0000000 62 1.1 uch #define HD64461_SYSTEM_REGSIZE 0x00001000 63 1.1 uch 64 1.1 uch #define HD64461_LCDC_REGBASE 0xb0001000 65 1.1 uch #define HD64461_LCDC_REGSIZE 0x00001000 66 1.1 uch 67 1.1 uch #define HD64461_PCMCIA_REGBASE 0xb0002000 68 1.1 uch #define HD64461_PCMCIA_REGSIZE 0x00001000 69 1.1 uch 70 1.1 uch #define HD64461_AFE_REGBASE 0xb0003000 71 1.1 uch #define HD64461_AFE_REGSIZE 0x00001000 72 1.1 uch 73 1.1 uch #define HD64461_GPIO_REGBASE 0xb0004000 74 1.1 uch #define HD64461_GPIO_REGSIZE 0x00001000 75 1.1 uch 76 1.1 uch #define HD64461_INTC_REGBASE 0xb0005000 77 1.1 uch #define HD64461_INTC_REGSIZE 0x00001000 78 1.1 uch 79 1.1 uch #define HD64461_TIMER_REGBASE 0xb0006000 80 1.1 uch #define HD64461_TIMER_REGSIZE 0x00001000 81 1.1 uch 82 1.1 uch #define HD64461_IRDA_REGBASE 0xb0007000 83 1.1 uch #define HD64461_IRDA_REGSIZE 0x00001000 84 1.1 uch 85 1.1 uch #define HD64461_UART_REGBASE 0xb0008000 86 1.1 uch #define HD64461_UART_REGSIZE 0x00001000 87 1.1 uch 88 1.1 uch /* 89 1.1 uch * System Configuration Register and STANBY Mode 90 1.1 uch */ 91 1.1 uch /* Stanby Control Register */ 92 1.1 uch #define HD64461_SYSSTBCR_REG16 0xb0000000 93 1.1 uch #define HD64461_SYSSTBCR_CKIO_STBY 0x2000 94 1.1 uch #define HD64461_SYSSTBCR_SAFECKE_IST 0x1000 95 1.1 uch #define HD64461_SYSSTBCR_SLCKE_IST 0x0800 96 1.1 uch #define HD64461_SYSSTBCR_SAFECKE_OST 0x0400 97 1.1 uch #define HD64461_SYSSTBCR_SLCKE_OST 0x0200 98 1.1 uch #define HD64461_SYSSTBCR_SMIAST 0x0100 99 1.1 uch #define HD64461_SYSSTBCR_SLCDST 0x0080 100 1.1 uch #define HD64461_SYSSTBCR_SPC0ST 0x0040 101 1.1 uch #define HD64461_SYSSTBCR_SPC1ST 0x0020 102 1.1 uch #define HD64461_SYSSTBCR_SAFEST 0x0010 103 1.1 uch #define HD64461_SYSSTBCR_STM0ST 0x0008 104 1.1 uch #define HD64461_SYSSTBCR_STM1ST 0x0004 105 1.1 uch #define HD64461_SYSSTBCR_SIRST 0x0002 106 1.1 uch #define HD64461_SYSSTBCR_SURTSD 0x0001 107 1.1 uch 108 1.1 uch /* System Configuration Register */ 109 1.1 uch #define HD64461_SYSSYSCR_REG16 0xb0000002 110 1.1 uch #define HD64461_SYSSYSCR_SCPU_BUS_IGAT 0x2000 111 1.1 uch #define HD64461_SYSSYSCR_SPTA_IR 0x0080 112 1.1 uch #define HD64461_SYSSYSCR_SPTA_TM 0x0040 113 1.1 uch #define HD64461_SYSSYSCR_SPTB_UR 0x0020 114 1.1 uch #define HD64461_SYSSYSCR_WAIT_CTL_SEL 0x0010 115 1.1 uch #define HD64461_SYSSYSCR_SMODE1 0x0002 116 1.1 uch #define HD64461_SYSSYSCR_SMODE0 0x0001 117 1.1 uch 118 1.1 uch /* CPU Data Bus Control Register */ 119 1.1 uch #define HD64461_SYSSCPUCR_REG16 0xb0000004 120 1.1 uch #define HD64461_SYSSCPUCR_SPDSTOF 0x8000 121 1.1 uch #define HD64461_SYSSCPUCR_SPDSTIG 0x4000 122 1.1 uch #define HD64461_SYSSCPUCR_SPCSTOF 0x2000 123 1.1 uch #define HD64461_SYSSCPUCR_SPCSTIG 0x1000 124 1.1 uch #define HD64461_SYSSCPUCR_SPBSTOF 0x0800 125 1.1 uch #define HD64461_SYSSCPUCR_SPBSTIG 0x0400 126 1.1 uch #define HD64461_SYSSCPUCR_SPASTOF 0x0200 127 1.1 uch #define HD64461_SYSSCPUCR_SPASTIG 0x0100 128 1.1 uch #define HD64461_SYSSCPUCR_SLCDSTIG 0x0080 129 1.1 uch #define HD64461_SYSSCPUCR_SCPU_CS56_EP 0x0040 130 1.1 uch #define HD64461_SYSSCPUCR_SCPU_CMD_EP 0x0020 131 1.1 uch #define HD64461_SYSSCPUCR_SCPU_ADDR_EP 0x0010 132 1.1 uch #define HD64461_SYSSCPUCR_SCPDPU 0x0008 133 1.1 uch #define HD64461_SYSSCPUCR_SCPU_A2319_EP 0x0001 134 1.3 uwe 135 1.3 uwe #endif /* !_HPCSH_DEV_HD64461REG_H_ */ 136
Indexes created Sat Sep 27 14:09:57 GMT 2025