1 /* $NetBSD: hd64461reg.h,v 1.4 2008/04/28 20:23:22 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _HPCSH_DEV_HD64461REG_H_ 33 #define _HPCSH_DEV_HD64461REG_H_ 34 35 #define SH3_AREA4_BASE 0xb0000000 36 #define SH3_AREA5_BASE 0xb4000000 37 #define SH3_AREA6_BASE 0xb8000000 38 39 /* HD64461 Address mapping (mapped to SH3 memory space) */ 40 41 /* SH3 Area 4 (Register, Framebuffer) */ 42 #define HD64461_REGBASE SH3_AREA4_BASE 43 #define HD64461_REGSIZE 0x02000000 44 #define HD64461_FBBASE (SH3_AREA4_BASE + 0x02000000) 45 #define HD64461_FBSIZE 0x02000000 46 #define HD64461_FBPAGESIZE 0x1000 47 48 /* SH3 Area 5 (PCC1 memory space) */ 49 #define HD64461_PCC1_MEMBASE SH3_AREA5_BASE 50 #define HD64461_PCC1_MEMSIZE 0x02000000 51 52 /* SH3 Area 6 (PCC0 memory, I/O space*/ 53 #define HD64461_PCC0_MEMBASE SH3_AREA6_BASE 54 #define HD64461_PCC0_MEMSIZE 0x02000000 55 #define HD64461_PCC0_IOBASE (SH3_AREA6_BASE + 0x02000000) 56 #define HD64461_PCC0_IOSIZE 0x02000000 57 58 /* 59 * Register mapping. 60 */ 61 #define HD64461_SYSTEM_REGBASE 0xb0000000 62 #define HD64461_SYSTEM_REGSIZE 0x00001000 63 64 #define HD64461_LCDC_REGBASE 0xb0001000 65 #define HD64461_LCDC_REGSIZE 0x00001000 66 67 #define HD64461_PCMCIA_REGBASE 0xb0002000 68 #define HD64461_PCMCIA_REGSIZE 0x00001000 69 70 #define HD64461_AFE_REGBASE 0xb0003000 71 #define HD64461_AFE_REGSIZE 0x00001000 72 73 #define HD64461_GPIO_REGBASE 0xb0004000 74 #define HD64461_GPIO_REGSIZE 0x00001000 75 76 #define HD64461_INTC_REGBASE 0xb0005000 77 #define HD64461_INTC_REGSIZE 0x00001000 78 79 #define HD64461_TIMER_REGBASE 0xb0006000 80 #define HD64461_TIMER_REGSIZE 0x00001000 81 82 #define HD64461_IRDA_REGBASE 0xb0007000 83 #define HD64461_IRDA_REGSIZE 0x00001000 84 85 #define HD64461_UART_REGBASE 0xb0008000 86 #define HD64461_UART_REGSIZE 0x00001000 87 88 /* 89 * System Configuration Register and STANBY Mode 90 */ 91 /* Stanby Control Register */ 92 #define HD64461_SYSSTBCR_REG16 0xb0000000 93 #define HD64461_SYSSTBCR_CKIO_STBY 0x2000 94 #define HD64461_SYSSTBCR_SAFECKE_IST 0x1000 95 #define HD64461_SYSSTBCR_SLCKE_IST 0x0800 96 #define HD64461_SYSSTBCR_SAFECKE_OST 0x0400 97 #define HD64461_SYSSTBCR_SLCKE_OST 0x0200 98 #define HD64461_SYSSTBCR_SMIAST 0x0100 99 #define HD64461_SYSSTBCR_SLCDST 0x0080 100 #define HD64461_SYSSTBCR_SPC0ST 0x0040 101 #define HD64461_SYSSTBCR_SPC1ST 0x0020 102 #define HD64461_SYSSTBCR_SAFEST 0x0010 103 #define HD64461_SYSSTBCR_STM0ST 0x0008 104 #define HD64461_SYSSTBCR_STM1ST 0x0004 105 #define HD64461_SYSSTBCR_SIRST 0x0002 106 #define HD64461_SYSSTBCR_SURTSD 0x0001 107 108 /* System Configuration Register */ 109 #define HD64461_SYSSYSCR_REG16 0xb0000002 110 #define HD64461_SYSSYSCR_SCPU_BUS_IGAT 0x2000 111 #define HD64461_SYSSYSCR_SPTA_IR 0x0080 112 #define HD64461_SYSSYSCR_SPTA_TM 0x0040 113 #define HD64461_SYSSYSCR_SPTB_UR 0x0020 114 #define HD64461_SYSSYSCR_WAIT_CTL_SEL 0x0010 115 #define HD64461_SYSSYSCR_SMODE1 0x0002 116 #define HD64461_SYSSYSCR_SMODE0 0x0001 117 118 /* CPU Data Bus Control Register */ 119 #define HD64461_SYSSCPUCR_REG16 0xb0000004 120 #define HD64461_SYSSCPUCR_SPDSTOF 0x8000 121 #define HD64461_SYSSCPUCR_SPDSTIG 0x4000 122 #define HD64461_SYSSCPUCR_SPCSTOF 0x2000 123 #define HD64461_SYSSCPUCR_SPCSTIG 0x1000 124 #define HD64461_SYSSCPUCR_SPBSTOF 0x0800 125 #define HD64461_SYSSCPUCR_SPBSTIG 0x0400 126 #define HD64461_SYSSCPUCR_SPASTOF 0x0200 127 #define HD64461_SYSSCPUCR_SPASTIG 0x0100 128 #define HD64461_SYSSCPUCR_SLCDSTIG 0x0080 129 #define HD64461_SYSSCPUCR_SCPU_CS56_EP 0x0040 130 #define HD64461_SYSSCPUCR_SCPU_CMD_EP 0x0020 131 #define HD64461_SYSSCPUCR_SCPU_ADDR_EP 0x0010 132 #define HD64461_SYSSCPUCR_SCPDPU 0x0008 133 #define HD64461_SYSSCPUCR_SCPU_A2319_EP 0x0001 134 135 #endif /* !_HPCSH_DEV_HD64461REG_H_ */ 136
Indexes created Thu Sep 25 15:09:46 GMT 2025