1 /* $NetBSD: hd64461uartreg.h,v 1.5 2008/04/28 20:23:22 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _HPCSH_DEV_HD64461UARTREG_H_ 33 #define _HPCSH_DEV_HD64461UARTREG_H_ 34 35 /* 36 * UART module Register 37 */ 38 39 /* Receiver Buffer Register (r) */ 40 #define HD64461_URBR_REG8 0xb0008000 41 /* Transmitter Buffer Register (w) */ 42 #define HD64461_UTBR_REG8 0xb0008000 43 /* Interrupt Enable Register */ 44 #define HD64461_UIER_REG8 0xb0008002 45 /* Interrupt Identification Register (r) */ 46 #define HD64461_UIIR_REG8 0xb0008004 47 /* FIFO Control Register (w) */ 48 #define HD64461_UFCR_REG8 0xb0008004 49 /* Line Control Register */ 50 #define HD64461_ULCR_REG8 0xb0008006 51 /* Modem Control Register */ 52 #define HD64461_UMCR_REG8 0xb0008008 53 /* Divisor Latch LSB */ 54 #define HD64461_UDLL_REG8 0xb0008000 55 /* Divisor Latch MSB */ 56 #define HD64461_UDLM_REG8 0xb0008002 57 /* Line Status Register */ 58 #define HD64461_ULSR_REG8 0xb000800a 59 /* Modem Status Register */ 60 #define HD64461_UMSR_REG8 0xb000800c 61 /* Scratch Pad Register */ 62 #define HD64461_USCR_REG8 0xb000800e 63 64 #define LSR_TXRDY 0x20 /* Transmitter buffer empty */ 65 66 #endif /* !_HPCSH_DEV_HD64461UARTREG_H_ */ 67
Indexes created Thu Sep 25 15:09:46 GMT 2025