1 /* $NetBSD: mca_machdep.c,v 1.44 2017/03/31 08:38:13 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc. 5 * Copyright (c) 1996-1999 Scott D. Telford. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Scott Telford <s.telford (at) ed.ac.uk> and Jaromir Dolecek 10 * <jdolecek (at) NetBSD.org>. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Machine-specific functions for MCA autoconfiguration. 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: mca_machdep.c,v 1.44 2017/03/31 08:38:13 msaitoh Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/device.h> 44 #include <sys/malloc.h> 45 #include <sys/systm.h> 46 #include <sys/syslog.h> 47 #include <sys/time.h> 48 #include <sys/kernel.h> 49 50 #include <machine/bioscall.h> 51 #include <machine/psl.h> 52 #include <sys/bus.h> 53 #include <machine/bus_private.h> 54 #include <machine/pio.h> 55 56 #include <dev/isa/isavar.h> 57 #include <dev/isa/isareg.h> 58 #include <dev/mca/mcavar.h> 59 #include <dev/mca/mcareg.h> 60 61 #include "isa.h" 62 #include "opt_mcaverbose.h" 63 64 /* System Configuration Block - this info is returned by the BIOS call */ 65 struct bios_config { 66 uint16_t count; 67 uint8_t model; 68 uint8_t submodel; 69 uint8_t bios_rev; 70 uint8_t feature1; 71 #define FEATURE_MCAISA 0x01 /* Machine contains both MCA and ISA bus */ 72 #define FEATURE_MCABUS 0x02 /* Machine has MCA bus instead of ISA */ 73 #define FEATURE_EBDA 0x04 /* Extended BIOS data area allocated */ 74 #define FEATURE_WAITEV 0x08 /* Wait for external event is supported */ 75 #define FEATURE_KBDINT 0x10 /* Keyboard intercept called by Int 09h */ 76 #define FEATURE_RTC 0x20 /* Real-time clock present */ 77 #define FEATURE_IC2 0x40 /* Second interrupt chip present */ 78 #define FEATURE_DMA3 0x80 /* DMA channel 3 used by hard disk BIOS */ 79 uint8_t feature2; 80 uint8_t pad[9]; 81 } __packed; 82 83 /* 84 * Used to encode DMA channel into ISA DMA cookie. We use upper 4 bits of 85 * ISA DMA cookie id_flags, it's unused. 86 */ 87 struct x86_isa_dma_cookie { 88 int id_flags; 89 /* We don't care about rest */ 90 }; 91 92 #ifdef UNUSED 93 static void _mca_bus_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, 94 bus_addr_t, bus_size_t, int); 95 #endif 96 97 /* 98 * For now, we use MCA DMA to 0-16M always. Some IBM PS/2 have 32bit MCA bus, 99 * but majority of them have 24bit only. 100 */ 101 #define MCA_DMA_BOUNCE_THRESHOLD (16 * 1024 * 1024) 102 103 struct x86_bus_dma_tag mca_bus_dma_tag = { 104 ._tag_needs_free = 0, 105 ._bounce_thresh = MCA_DMA_BOUNCE_THRESHOLD, 106 ._bounce_alloc_lo = 0, 107 ._bounce_alloc_hi = MCA_DMA_BOUNCE_THRESHOLD, 108 ._may_bounce = NULL, 109 }; 110 111 /* Updated in mca_busprobe() if appropriate. */ 112 int MCA_system = 0; 113 114 /* Used to kick MCA DMA controller */ 115 #define DMA_CMD 0x18 /* command the controller */ 116 #define DMA_EXEC 0x1A /* tell controller how to do things */ 117 static bus_space_handle_t dmacmdh, dmaexech; 118 static bus_space_tag_t dmaiot; 119 120 /* 121 * MCA DMA controller commands. The exact sense of individual bits 122 * are from Tymm Twillman <tymm (at) computer.org>, who worked on Linux MCA DMA 123 * support. 124 */ 125 #define DMACMD_SET_IO 0x00 /* set port (16bit) for i/o transfer */ 126 #define DMACMD_SET_ADDR 0x20 /* set addr (24bit) for i/o transfer */ 127 #define DMACMD_GET_ADDR 0x30 /* get addr (24bit) for i/o transfer */ 128 #define DMACMD_SET_CNT 0x40 /* set memory size for DMA (16b) */ 129 #define DMACMD_GET_CNT 0x50 /* get count of remaining bytes in DMA*/ 130 #define DMACMD_GET_STATUS 0x60 /* ?? */ 131 #define DMACMD_SET_MODE 0x70 /* set DMA mode */ 132 # define DMACMD_MODE_XFER 0x04 /* do transfer, read by default */ 133 # define DMACMD_MODE_READ 0x08 /* read transfer */ 134 # define DMACMD_MODE_WRITE 0x00 /* write transfer */ 135 # define DMACMD_MODE_IOPORT 0x01 /* DMA from/to IO register */ 136 # define DMACMD_MODE_16BIT 0x40 /* 16bit transfers (default 8bit) */ 137 #define DMACMD_SET_ARBUS 0x80 /* ?? */ 138 #define DMACMD_MASK 0x90 /* command mask */ 139 #define DMACMD_RESET_MASK 0xA0 /* reset */ 140 #define DMACMD_MASTER_CLEAR 0xD0 /* ?? */ 141 142 /* 143 * Map the MCA DMA controller registers. 144 */ 145 void 146 mca_attach_hook(device_t parent, device_t self, 147 struct mcabus_attach_args *mba) 148 { 149 dmaiot = mba->mba_iot; 150 151 if (bus_space_map(dmaiot, DMA_CMD, 1, 0, &dmacmdh) 152 || bus_space_map(dmaiot, DMA_EXEC, 1, 0, &dmaexech)) 153 panic("mca: couldn't map DMA registers"); 154 } 155 156 /* 157 * Read value of MCA POS register "reg" in slot "slot". 158 */ 159 160 int 161 mca_conf_read(mca_chipset_tag_t mc, int slot, int reg) 162 { 163 int data; 164 165 slot &= 7; /* slot must be in range 0-7 */ 166 outb(MCA_MB_SETUP_REG, 0xff); /* ensure m/board setup is disabled */ 167 outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET); 168 data = inb(MCA_POS_REG(reg)); 169 outb(MCA_ADAP_SETUP_REG, 0); 170 return data; 171 } 172 173 174 /* 175 * Write "data" to MCA POS register "reg" in slot "slot". 176 */ 177 178 void 179 mca_conf_write(mca_chipset_tag_t mc, int slot, int reg, int data) 180 { 181 slot&=7; /* slot must be in range 0-7 */ 182 outb(MCA_MB_SETUP_REG, 0xff); /* ensure m/board setup is disabled */ 183 outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET); 184 outb(MCA_POS_REG(reg), data); 185 outb(MCA_ADAP_SETUP_REG, 0); 186 } 187 188 #if NISA <= 0 189 #error mca_intr_(dis)establish: needs ISA to be configured into kernel 190 #endif 191 192 #if 0 193 const struct evcnt * 194 mca_intr_establish(mca_chipset_tag_t mc, mca_intr_handle_t ih) 195 { 196 197 /* XXX for now, no evcnt parent reported */ 198 return NULL; 199 } 200 #endif 201 202 void * 203 mca_intr_establish(mca_chipset_tag_t mc, mca_intr_handle_t ih, 204 int level, int (*func)(void *), void *arg) 205 { 206 if (ih == 0 || ih >= NUM_LEGACY_IRQS || ih == 2) 207 panic("mca_intr_establish: bogus handle 0x%x", ih); 208 209 /* MCA interrupts are always level-triggered */ 210 return isa_intr_establish(NULL, ih, IST_LEVEL, level, func, arg); 211 } 212 213 void 214 mca_intr_disestablish(mca_chipset_tag_t mc, void *cookie) 215 { 216 isa_intr_disestablish(NULL, cookie); 217 } 218 219 220 /* 221 * Handle a NMI. 222 * return true to panic system, false to ignore. 223 */ 224 void 225 mca_nmi(void) 226 { 227 /* 228 * PS/2 MCA devices can generate NMIs - we can find out which 229 * slot generated it from the POS registers. 230 */ 231 232 int slot, mcanmi=0; 233 234 /* if there is no MCA bus, call x86_nmi() */ 235 if (!MCA_system) 236 goto out; 237 238 /* ensure motherboard setup is disabled */ 239 outb(MCA_MB_SETUP_REG, 0xff); 240 241 /* find if an MCA slot has the CHCK bit asserted (low) in POS 5 */ 242 for(slot=0; slot<MCA_MAX_SLOTS; slot++) { 243 outb(MCA_ADAP_SETUP_REG, slot | MCA_ADAP_SET); 244 if ((inb(MCA_POS_REG(5)) & MCA_POS5_CHCK) == 0) { 245 mcanmi = 1; 246 /* find if CHCK status is available in POS 6/7 */ 247 if((inb(MCA_POS_REG(5)) & MCA_POS5_CHCK_STAT) == 0) 248 log(LOG_CRIT, "MCA NMI: slot %d, POS6=0x%02x, POS7=0x%02x\n", 249 slot+1, inb(MCA_POS_REG(6)), 250 inb(MCA_POS_REG(7))); 251 else 252 log(LOG_CRIT, "MCA NMI: slot %d\n", slot+1); 253 } 254 } 255 outb(MCA_ADAP_SETUP_REG, 0); 256 257 out: 258 if (!mcanmi) { 259 /* no CHCK bits asserted, assume ISA NMI */ 260 x86_nmi(); 261 } 262 } 263 264 /* 265 * We can obtain the information about MCA bus presence via 266 * GET CONFIGURATION BIOS call - int 0x15, function 0xc0. 267 * The call returns a pointer to memory place with the configuration block 268 * in es:bx (on AT-compatible, e.g. all we care about, computers). 269 * 270 * Configuration block contains block length (2 bytes), model 271 * number (1 byte), submodel number (1 byte), BIOS revision 272 * (1 byte) and up to 5 feature bytes. We only care about 273 * first feature byte. 274 */ 275 void 276 mca_busprobe(void) 277 { 278 struct bioscallregs regs; 279 struct bios_config *scp; 280 paddr_t paddr; 281 char buf[80]; 282 283 memset(®s, 0, sizeof(regs)); 284 regs.AH = 0xc0; 285 bioscall(0x15, ®s); 286 287 if ((regs.EFLAGS & PSL_C) || regs.AH != 0) { 288 aprint_verbose("BIOS CFG: Not supported. Not AT-compatible?\n"); 289 return; 290 } 291 292 paddr = (regs.ES << 4) + regs.BX; 293 scp = (struct bios_config *)ISA_HOLE_VADDR(paddr); 294 295 snprintb(buf, sizeof(buf), 296 "\20" 297 "\01MCA+ISA" 298 "\02MCA" 299 "\03EBDA" 300 "\04WAITEV" 301 "\05KBDINT" 302 "\06RTC" 303 "\07IC2" 304 "\010DMA3B" 305 "\011res" 306 "\012DSTR" 307 "\013n8042" 308 "\014CPUF" 309 "\015MMF" 310 "\016GPDF" 311 "\017KBDF" 312 "\020DMA32\n", (scp->feature2 << 8) | scp->feature1); 313 314 aprint_verbose("BIOS CFG: Model-SubM-Rev: %02x-%02x-%02x, %s\n", 315 scp->model, scp->submodel, scp->bios_rev, buf); 316 317 MCA_system = (scp->feature1 & FEATURE_MCABUS) ? 1 : 0; 318 } 319 320 #define PORT_DISKLED 0x92 321 #define DISKLED_ON 0x40 322 323 /* 324 * Light disk busy LED on IBM PS/2. 325 */ 326 void 327 mca_disk_busy(void) 328 { 329 outb(PORT_DISKLED, inb(PORT_DISKLED) | DISKLED_ON); 330 } 331 332 /* 333 * Turn off disk LED on IBM PS/2. 334 */ 335 void 336 mca_disk_unbusy(void) 337 { 338 outb(PORT_DISKLED, inb(PORT_DISKLED) & ~DISKLED_ON); 339 } 340 341 /* 342 * -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- 343 * MCA DMA specific stuff. We use ISA routines for bulk of the work, 344 * since MCA shares much of the charasteristics with it. We just hook 345 * the DMA channel initialization and kick MCA DMA controller appropriately. 346 * -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=- 347 */ 348 349 #ifdef UNUSED 350 /* 351 * Synchronize a MCA DMA map. 352 */ 353 static void 354 _mca_bus_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, bus_addr_t offset, 355 bus_size_t len, int ops) 356 { 357 struct x86_isa_dma_cookie *cookie; 358 bus_addr_t phys; 359 bus_size_t cnt; 360 int dmach, mode; 361 362 _bus_dmamap_sync(t, map, offset, len, ops); 363 364 /* 365 * Don't do anything if not using the DMA controller. 366 */ 367 if ((map->_dm_flags & _MCABUS_DMA_USEDMACTRL) == 0) 368 return; 369 370 /* 371 * Don't do anything if not PRE* operation, allow only 372 * one of PREREAD and PREWRITE. 373 */ 374 if (ops != BUS_DMASYNC_PREREAD && ops != BUS_DMASYNC_PREWRITE) 375 return; 376 377 cookie = (struct x86_isa_dma_cookie *)map->_dm_cookie; 378 dmach = (cookie->id_flags & 0xf0) >> 4; 379 380 phys = map->dm_segs[0].ds_addr; 381 cnt = map->dm_segs[0].ds_len; 382 383 mode = DMACMD_MODE_XFER; 384 mode |= (ops == BUS_DMASYNC_PREREAD) 385 ? DMACMD_MODE_READ : DMACMD_MODE_WRITE; 386 if (map->_dm_flags & MCABUS_DMA_IOPORT) 387 mode |= DMACMD_MODE_IOPORT; 388 389 /* Use 16bit DMA if requested */ 390 if (map->_dm_flags & MCABUS_DMA_16BIT) { 391 #ifdef DIAGNOSTIC 392 if ((cnt % 2) != 0) { 393 panic("_mca_bus_dmamap_sync: 16bit DMA and cnt %lu odd", 394 cnt); 395 } 396 #endif 397 mode |= DMACMD_MODE_16BIT; 398 cnt /= 2; 399 } 400 401 /* 402 * Initialize the MCA DMA controller appropriately. The exact 403 * sequence to setup the controller is taken from Minix. 404 */ 405 406 /* Disable access to DMA channel. */ 407 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_MASK | dmach); 408 409 /* Set the transfer mode. */ 410 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_SET_MODE | dmach); 411 bus_space_write_1(dmaiot, dmaexech, 0, mode); 412 413 /* Set the address byte pointer. */ 414 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_SET_ADDR | dmach); 415 /* address bits 0..7 */ 416 bus_space_write_1(dmaiot, dmaexech, 0, (phys >> 0) & 0xff); 417 /* address bits 8..15 */ 418 bus_space_write_1(dmaiot, dmaexech, 0, (phys >> 8) & 0xff); 419 /* address bits 16..23 */ 420 bus_space_write_1(dmaiot, dmaexech, 0, (phys >> 16) & 0xff); 421 422 /* Set the count byte pointer */ 423 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_SET_CNT | dmach); 424 /* count bits 0..7 */ 425 bus_space_write_1(dmaiot, dmaexech, 0, ((cnt - 1) >> 0) & 0xff); 426 /* count bits 8..15 */ 427 bus_space_write_1(dmaiot, dmaexech, 0, ((cnt - 1) >> 8) & 0xff); 428 429 /* Enable access to DMA channel. */ 430 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_RESET_MASK | dmach); 431 } 432 #endif 433 434 /* 435 * Allocate a DMA map, and set up DMA channel. 436 */ 437 int 438 mca_dmamap_create(bus_dma_tag_t t, bus_size_t size, int flags, 439 bus_dmamap_t *dmamp, int dmach) 440 { 441 int error; 442 struct x86_isa_dma_cookie *cookie; 443 444 #ifdef DEBUG 445 /* Sanity check */ 446 if (dmach < 0 || dmach >= 16) { 447 printf("mcadma_create: invalid DMA channel %d\n", 448 dmach); 449 return (EINVAL); 450 } 451 452 if (size > 65536) { 453 panic("mca_dmamap_create: dmamap sz %ld > 65536", 454 (long) size); 455 } 456 #endif 457 458 /* 459 * MCA DMA transfer can be maximum 65536 bytes long and must 460 * be in one chunk. No specific boundary constraints are present. 461 */ 462 if ((error = bus_dmamap_create(t, size, 1, 65536, 0, flags, dmamp))) 463 return (error); 464 465 cookie = (struct x86_isa_dma_cookie *) (*dmamp)->_dm_cookie; 466 467 if (cookie == NULL) { 468 /* 469 * Allocate our cookie if not yet done. 470 */ 471 cookie = malloc(sizeof(struct x86_bus_dma_cookie), M_DMAMAP, 472 ((flags & BUS_DMA_NOWAIT) ? M_NOWAIT : M_WAITOK) | M_ZERO); 473 if (cookie == NULL) { 474 475 return ENOMEM; 476 } 477 (*dmamp)->_dm_cookie = cookie; 478 } 479 480 481 /* Encode DMA channel */ 482 cookie->id_flags &= 0x0f; 483 cookie->id_flags |= dmach << 4; 484 485 /* Mark the dmamap as using DMA controller. Some devices 486 * drive DMA themselves, and don't need the MCA DMA controller. 487 * To distinguish the two, use a flag for dmamaps which use the DMA 488 * controller. 489 */ 490 (*dmamp)->_dm_flags |= _MCABUS_DMA_USEDMACTRL; 491 492 return (0); 493 } 494 495 /* 496 * Set I/O port for DMA. Implemented separately from _mca_bus_dmamap_sync() 497 * so that it's available for one-shot setup. 498 */ 499 void 500 mca_dma_set_ioport(int dma, uint16_t port) 501 { 502 /* Disable access to dma channel. */ 503 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_MASK | dma); 504 505 /* Set I/O port to use for DMA */ 506 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_SET_IO | dma); 507 bus_space_write_1(dmaiot, dmaexech, 0, port & 0xff); 508 bus_space_write_1(dmaiot, dmaexech, 0, (port >> 8) & 0xff); 509 510 /* Enable access to DMA channel. */ 511 bus_space_write_1(dmaiot, dmacmdh, 0, DMACMD_RESET_MASK | dma); 512 } 513
Indexes created Sat Sep 20 22:09:52 GMT 2025