gcscide.c revision 1.1
1/* $NetBSD: gcscide.c,v 1.1 2007/06/27 23:02:53 xtraeme Exp $ */ 2 3/* 4 * Copyright (c) 2007 The NetBSD Foundation. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to the NetBSD Foundation 8 * by Juan Romero Pardines. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Juan Romero Pardines 21 * for the NetBSD Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * Driver for the National Semiconductor/AMD CS5535 Companion Controller. 41 * Usually this comes with an AMD Geode GX CPU. 42 * 43 * Datasheet at: 44 * 45 * http://www.amd.com/files/connectivitysolutions/geode/geode_gx/31506_cs5535_databook.pdf 46 */ 47 48#include <sys/cdefs.h> 49__KERNEL_RCSID(0, "$NetBSD: gcscide.c,v 1.1 2007/06/27 23:02:53 xtraeme Exp $"); 50 51#include <sys/param.h> 52#include <sys/systm.h> 53 54#include <dev/pci/pcivar.h> 55#include <dev/pci/pcidevs.h> 56#include <dev/pci/pciidereg.h> 57#include <dev/pci/pciidevar.h> 58 59#include <machine/cpufunc.h> 60 61#define GCSCIDE_MSR_ATAC_BASE 0x51300000 62#define GCSCIDE_ATAC_GLD_MSR_CAP (GCSCIDE_MSR_ATAC_BASE + 0) 63#define GCSCIDE_ATAC_GLD_MSR_CONFIG (GCSCIDE_MSR_ATAC_BASE + 0x01) 64#define GCSCIDE_ATAC_GLD_MSR_SMI (GCSCIDE_MSR_ATAC_BASE + 0x02) 65#define GCSCIDE_ATAC_GLD_MSR_ERROR (GCSCIDE_MSR_ATAC_BASE + 0x03) 66#define GCSCIDE_ATAC_GLD_MSR_PM (GCSCIDE_MSR_ATAC_BASE + 0x04) 67#define GCSCIDE_ATAC_GLD_MSR_DIAG (GCSCIDE_MSR_ATAC_BASE + 0x05) 68#define GCSCIDE_ATAC_IO_BAR (GCSCIDE_MSR_ATAC_BASE + 0x08) 69#define GCSCIDE_ATAC_RESET (GCSCIDE_MSR_ATAC_BASE + 0x10) 70#define GCSCIDE_ATAC_CH0D0_PIO (GCSCIDE_MSR_ATAC_BASE + 0x20) 71#define GCSCIDE_ATAC_CH0D0_DMA (GCSCIDE_MSR_ATAC_BASE + 0x21) 72#define GCSCIDE_ATAC_CH0D1_PIO (GCSCIDE_MSR_ATAC_BASE + 0x22) 73#define GCSCIDE_ATAC_CH0D1_DMA (GCSCIDE_MSR_ATAC_BASE + 0x23) 74#define GCSCIDE_ATAC_PCI_ABRTERR (GCSCIDE_MSR_ATAC_BASE + 0x24) 75#define GCSCIDE_ATAC_BM0_CMD_PRIM 0x00 76#define GCSCIDE_ATAC_BM0_STS_PRIM 0x02 77#define GCSCIDE_ATAC_BM0_PRD 0x04 78#define GCSCIDE_PIO_FORMAT 0x80000000UL 79 80static int gcscide_match(struct device *, struct cfdata *, void *); 81static void gcscide_attach(struct device *, struct device *, void *); 82 83static void gcscide_chip_map(struct pciide_softc *, struct pci_attach_args *); 84static void gcscide_setup_channel(struct ata_channel *); 85 86/* PIO Format 1 timings */ 87static const uint32_t gcscide_pio_timings[] = { 88 0xf7f4f7f4, /* PIO Mode 0 */ 89 0x53f3f173, /* PIO Mode 1 */ 90 0x13f18141, /* PIO Mode 2 */ 91 0x51315131, /* PIO Mode 3 */ 92 0x11311131 /* PIO Mode 4 */ 93}; 94 95static const uint32_t gcscide_mdma_timings[] = { 96 0x7f0ffff3, /* MDMA Mode 0 */ 97 0x7f035352, /* MDMA Mode 1 */ 98 0x7f024241 /* MDMA Mode 2 */ 99}; 100 101static const uint32_t gcscide_udma_timings[] = { 102 0x7f7436a1, /* Ultra DMA Mode 0 */ 103 0x7f733481, /* Ultra DMA Mode 1 */ 104 0x7f723261, /* Ultra DMA Mode 2 */ 105 0x7f713161, /* Ultra DMA Mode 3 */ 106 0x7f703061 /* Ultra DMA Mode 4 */ 107}; 108 109CFATTACH_DECL(gcscide, sizeof(struct pciide_softc), 110 gcscide_match, gcscide_attach, NULL, NULL); 111 112static const struct pciide_product_desc pciide_gcscide_products[] = { 113 { 114 PCI_PRODUCT_NS_CS5535_IDE, 115 0, 116 "National Semiconductor/AMD CS5535 IDE Controller", 117 gcscide_chip_map 118 }, 119 { 0, 0, NULL, NULL } 120}; 121 122static int 123gcscide_match(struct device *parent, struct cfdata *cfdata, void *aux) 124{ 125 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 126 127 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 128 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 129 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE && 130 pciide_lookup_product(pa->pa_id, pciide_gcscide_products)) 131 return 2; 132 return 0; 133} 134 135static void 136gcscide_attach(struct device *parent, struct device *self, void *aux) 137{ 138 struct pci_attach_args *pa = aux; 139 struct pciide_softc *sc = (struct pciide_softc *)self; 140 141 pciide_common_attach(sc, pa, 142 pciide_lookup_product(pa->pa_id, pciide_gcscide_products)); 143} 144 145static void 146gcscide_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 147{ 148 pcireg_t interface; 149 bus_size_t cmdsize, ctlsize; 150 151 if (pciide_chipen(sc, pa) == 0) 152 return; 153 154 aprint_verbose("%s: bus-master DMA support present", 155 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 156 pciide_mapreg_dma(sc, pa); 157 aprint_verbose("\n"); 158 159 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 160 if (sc->sc_dma_ok) { 161 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 162 sc->sc_wdcdev.irqack = pciide_irqack; 163 } 164 165 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 166 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 167 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 168 sc->sc_wdcdev.sc_atac.atac_set_modes = gcscide_setup_channel; 169 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 170 sc->sc_wdcdev.sc_atac.atac_nchannels = 1; 171 172 interface = PCI_INTERFACE(pa->pa_class); 173 174 wdc_allocate_regs(&sc->sc_wdcdev); 175 176 if (pciide_chansetup(sc, 0, interface) == 0) 177 return; 178 179 pciide_mapchan(pa, &sc->pciide_channels[0], interface, 180 &cmdsize, &ctlsize, pciide_pci_intr); 181} 182 183static void 184gcscide_setup_channel(struct ata_channel *chp) 185{ 186 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 187 struct ata_drive_datas *drvp; 188 uint64_t reg = 0; 189 int drive, s; 190 191 pciide_channel_dma_setup(cp); 192 193 for (drive = 0; drive < 2; drive++) { 194 drvp = &chp->ch_drive[drive]; 195 if ((drvp->drive_flags & DRIVE) == 0) 196 continue; 197 if ((drvp->drive_flags & DRIVE_UDMA) || 198 (drvp->drive_flags & DRIVE_DMA)) { 199 reg = rdmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 200 GCSCIDE_ATAC_CH0D0_DMA); 201 202 /* high 32 bits */ 203 reg = (reg << 32); 204 /* Preserve PIO Format bit */ 205 reg &= GCSCIDE_PIO_FORMAT; 206 } 207 208 if (drvp->drive_flags & DRIVE_UDMA) { 209 s = splbio(); 210 drvp->drive_flags &= ~DRIVE_DMA; 211 splx(s); 212 /* Set UDMA and MDMA timings */ 213 reg |= gcscide_udma_timings[drvp->UDMA_mode]; 214 reg |= gcscide_mdma_timings[drvp->DMA_mode]; 215 216 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 217 GCSCIDE_ATAC_CH0D0_DMA, reg); 218 219 } else if (drvp->drive_flags & DRIVE_DMA) { 220 /* 221 * Disable Ultra DMA and set a MDMA mode. 222 */ 223 if (reg & gcscide_udma_timings[drvp->UDMA_mode]) 224 reg &= ~gcscide_udma_timings[drvp->UDMA_mode]; 225 226 reg |= gcscide_mdma_timings[drvp->DMA_mode]; 227 228 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 229 GCSCIDE_ATAC_CH0D0_DMA, reg); 230 } else { 231 /* 232 * Set PIO Format 1 timings. 233 */ 234 reg = rdmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 235 GCSCIDE_ATAC_CH0D0_DMA); 236 reg = (reg << 32); 237 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_DMA : 238 GCSCIDE_ATAC_CH0D0_DMA, reg | GCSCIDE_PIO_FORMAT); 239 } 240 /* Set PIO mode and timing */ 241 wrmsr(drive ? GCSCIDE_ATAC_CH0D1_PIO : GCSCIDE_ATAC_CH0D1_PIO, 242 gcscide_pio_timings[drvp->PIO_mode]); 243 } 244} 245