1 /* $NetBSD: gscpcib.c,v 1.20 2021/08/07 16:18:55 thorpej Exp $ */ 2 /* $OpenBSD: gscpcib.c,v 1.3 2004/10/05 19:02:33 grange Exp $ */ 3 /* 4 * Copyright (c) 2004 Alexander Yurchenko <grange (at) openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Special driver for the National Semiconductor Geode SC1100 PCI-ISA bridge 21 * that attaches instead of pcib(4). In addition to the core pcib(4) 22 * functionality this driver provides support for the GPIO interface. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: gscpcib.c,v 1.20 2021/08/07 16:18:55 thorpej Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/device.h> 31 #include <sys/gpio.h> 32 #include <sys/kernel.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 40 #include <dev/gpio/gpiovar.h> 41 42 #include <i386/pci/gscpcibreg.h> 43 #include <arch/x86/pci/pcibvar.h> 44 45 #include "gpio.h" 46 47 struct gscpcib_softc { 48 struct pcib_softc sc_pcib; 49 50 bool sc_gpio_present; 51 device_t sc_gpiobus; 52 53 /* GPIO interface */ 54 bus_space_tag_t sc_gpio_iot; 55 bus_space_handle_t sc_gpio_ioh; 56 struct gpio_chipset_tag sc_gpio_gc; 57 gpio_pin_t sc_gpio_pins[GSCGPIO_NPINS]; 58 }; 59 60 int gscpcib_match(device_t, cfdata_t, void *); 61 void gscpcib_attach(device_t, device_t, void *); 62 int gscpcib_detach(device_t, int); 63 int gscpcib_rescan(device_t, const char *, const int *); 64 void gscpcib_childdetached(device_t, device_t); 65 66 int gscpcib_gpio_pin_read(void *, int); 67 void gscpcib_gpio_pin_write(void *, int, int); 68 void gscpcib_gpio_pin_ctl(void *, int, int); 69 70 CFATTACH_DECL3_NEW(gscpcib, sizeof(struct gscpcib_softc), 71 gscpcib_match, gscpcib_attach, gscpcib_detach, NULL, gscpcib_rescan, 72 gscpcib_childdetached, DVF_DETACH_SHUTDOWN); 73 74 extern struct cfdriver gscpcib_cd; 75 76 void 77 gscpcib_childdetached(device_t self, device_t child) 78 { 79 struct gscpcib_softc *sc = device_private(self); 80 81 if (sc->sc_gpiobus == child) 82 sc->sc_gpiobus = NULL; 83 else 84 pcibchilddet(self, child); 85 } 86 87 int 88 gscpcib_rescan(device_t self, const char *ifattr, const int *loc) 89 { 90 #if NGPIO > 0 91 struct gscpcib_softc *sc = device_private(self); 92 93 /* Attach GPIO framework */ 94 if (sc->sc_gpio_present && ifattr_match(ifattr, "gpiobus") && 95 sc->sc_gpiobus == NULL) { 96 struct gpiobus_attach_args gba; 97 98 gba.gba_gc = &sc->sc_gpio_gc; 99 gba.gba_pins = sc->sc_gpio_pins; 100 gba.gba_npins = GSCGPIO_NPINS; 101 102 sc->sc_gpiobus = config_found(self, &gba, gpiobus_print, 103 CFARGS(.iattr = "gpiobus")); 104 return 0; 105 } 106 #endif 107 108 return pcibrescan(self, ifattr, loc); 109 } 110 111 int 112 gscpcib_match(device_t parent, cfdata_t match, void *aux) 113 { 114 struct pci_attach_args *pa = aux; 115 116 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 117 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 118 return (0); 119 120 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 121 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SC1100_ISA) 122 return (2); /* supersede pcib(4) */ 123 124 return (0); 125 } 126 127 void 128 gscpcib_attach(device_t parent, device_t self, void *aux) 129 { 130 struct gscpcib_softc *sc = device_private(self); 131 struct pci_attach_args *pa = aux; 132 pcireg_t gpiobase; 133 int i; 134 135 /* Map GPIO I/O space */ 136 gpiobase = pci_conf_read(pa->pa_pc, pa->pa_tag, GSCGPIO_BASE); 137 sc->sc_gpio_iot = pa->pa_iot; 138 if (bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(gpiobase), 139 GSCGPIO_SIZE, 0, &sc->sc_gpio_ioh)) { 140 printf(": failed to map GPIO I/O space"); 141 goto corepcib; 142 } 143 144 /* Initialize pins array */ 145 for (i = 0; i < GSCGPIO_NPINS; i++) { 146 sc->sc_gpio_pins[i].pin_num = i; 147 sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT | 148 GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | 149 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 150 GPIO_PIN_PULLUP; 151 152 /* safe defaults */ 153 sc->sc_gpio_pins[i].pin_flags = GPIO_PIN_TRISTATE; 154 sc->sc_gpio_pins[i].pin_state = GPIO_PIN_LOW; 155 gscpcib_gpio_pin_ctl(sc, i, sc->sc_gpio_pins[i].pin_flags); 156 gscpcib_gpio_pin_write(sc, i, sc->sc_gpio_pins[i].pin_state); 157 } 158 159 /* Create controller tag */ 160 sc->sc_gpio_gc.gp_cookie = sc; 161 sc->sc_gpio_gc.gp_pin_read = gscpcib_gpio_pin_read; 162 sc->sc_gpio_gc.gp_pin_write = gscpcib_gpio_pin_write; 163 sc->sc_gpio_gc.gp_pin_ctl = gscpcib_gpio_pin_ctl; 164 165 sc->sc_gpio_present = true; 166 167 corepcib: 168 /* Provide core pcib(4) functionality */ 169 pcibattach(parent, self, aux); 170 171 gscpcib_rescan(self, "gpiobus", NULL); 172 } 173 174 int 175 gscpcib_detach(device_t self, int flags) 176 { 177 int rc; 178 struct gscpcib_softc *sc = device_private(self); 179 180 if ((rc = config_detach_children(self, flags)) != 0) 181 return rc; 182 183 if ((rc = pcibdetach(self, flags)) != 0) 184 return rc; 185 186 if (sc->sc_gpio_present) 187 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, GSCGPIO_SIZE); 188 189 return rc; 190 } 191 192 static inline void 193 gscpcib_gpio_pin_select(struct gscpcib_softc *sc, int pin) 194 { 195 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, GSCGPIO_SEL, pin); 196 } 197 198 int 199 gscpcib_gpio_pin_read(void *arg, int pin) 200 { 201 struct gscpcib_softc *sc = arg; 202 int reg, shift; 203 uint32_t data; 204 205 reg = (pin < 32 ? GSCGPIO_GPDI0 : GSCGPIO_GPDI1); 206 shift = pin % 32; 207 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 208 209 return ((data >> shift) & 0x1); 210 } 211 212 void 213 gscpcib_gpio_pin_write(void *arg, int pin, int value) 214 { 215 struct gscpcib_softc *sc = arg; 216 int reg, shift; 217 uint32_t data; 218 219 reg = (pin < 32 ? GSCGPIO_GPDO0 : GSCGPIO_GPDO1); 220 shift = pin % 32; 221 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 222 if (value == 0) 223 data &= ~(1 << shift); 224 else if (value == 1) 225 data |= (1 << shift); 226 227 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 228 } 229 230 void 231 gscpcib_gpio_pin_ctl(void *arg, int pin, int flags) 232 { 233 struct gscpcib_softc *sc = arg; 234 uint32_t conf; 235 236 gscpcib_gpio_pin_select(sc, pin); 237 conf = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 238 GSCGPIO_CONF); 239 240 conf &= ~(GSCGPIO_CONF_OUTPUTEN | GSCGPIO_CONF_PUSHPULL | 241 GSCGPIO_CONF_PULLUP); 242 if ((flags & GPIO_PIN_TRISTATE) == 0) 243 conf |= GSCGPIO_CONF_OUTPUTEN; 244 if (flags & GPIO_PIN_PUSHPULL) 245 conf |= GSCGPIO_CONF_PUSHPULL; 246 if (flags & GPIO_PIN_PULLUP) 247 conf |= GSCGPIO_CONF_PULLUP; 248 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 249 GSCGPIO_CONF, conf); 250 } 251
Indexes created Mon Sep 22 10:09:38 GMT 2025