gscpcib.c revision 1.17
1 /* $NetBSD: gscpcib.c,v 1.17 2011/09/04 15:05:26 sborrill Exp $ */ 2 /* $OpenBSD: gscpcib.c,v 1.3 2004/10/05 19:02:33 grange Exp $ */ 3 /* 4 * Copyright (c) 2004 Alexander Yurchenko <grange (at) openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Special driver for the National Semiconductor Geode SC1100 PCI-ISA bridge 21 * that attaches instead of pcib(4). In addition to the core pcib(4) 22 * functionality this driver provides support for the GPIO interface. 23 */ 24 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: gscpcib.c,v 1.17 2011/09/04 15:05:26 sborrill Exp $"); 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/device.h> 31 #include <sys/gpio.h> 32 #include <sys/kernel.h> 33 34 #include <sys/bus.h> 35 36 #include <dev/pci/pcireg.h> 37 #include <dev/pci/pcivar.h> 38 #include <dev/pci/pcidevs.h> 39 40 #include <dev/gpio/gpiovar.h> 41 42 #include <i386/pci/gscpcibreg.h> 43 #include <arch/x86/pci/pcibvar.h> 44 45 struct gscpcib_softc { 46 struct pcib_softc sc_pcib; 47 48 bool sc_gpio_present; 49 device_t sc_gpiobus; 50 51 /* GPIO interface */ 52 bus_space_tag_t sc_gpio_iot; 53 bus_space_handle_t sc_gpio_ioh; 54 struct gpio_chipset_tag sc_gpio_gc; 55 gpio_pin_t sc_gpio_pins[GSCGPIO_NPINS]; 56 }; 57 58 int gscpcib_match(device_t, cfdata_t, void *); 59 void gscpcib_attach(device_t, device_t, void *); 60 int gscpcib_detach(device_t, int); 61 int gscpcib_rescan(device_t, const char *, const int *); 62 void gscpcib_childdetached(device_t, device_t); 63 64 int gscpcib_gpio_pin_read(void *, int); 65 void gscpcib_gpio_pin_write(void *, int, int); 66 void gscpcib_gpio_pin_ctl(void *, int, int); 67 68 CFATTACH_DECL3_NEW(gscpcib, sizeof(struct gscpcib_softc), 69 gscpcib_match, gscpcib_attach, gscpcib_detach, NULL, gscpcib_rescan, 70 gscpcib_childdetached, DVF_DETACH_SHUTDOWN); 71 72 extern struct cfdriver gscpcib_cd; 73 74 void 75 gscpcib_childdetached(device_t self, device_t child) 76 { 77 struct gscpcib_softc *sc = device_private(self); 78 79 if (sc->sc_gpiobus == child) 80 sc->sc_gpiobus = NULL; 81 else 82 pcibchilddet(self, child); 83 } 84 85 int 86 gscpcib_rescan(device_t self, const char *ifattr, const int *loc) 87 { 88 #if NGPIO > 0 89 struct gscpcib_softc *sc = device_private(self); 90 91 /* Attach GPIO framework */ 92 if (sc->sc_gpio_present && ifattr_match(ifattr, "gpiobus") && 93 sc->sc_gpiobus == NULL) { 94 struct gpiobus_attach_args gba; 95 96 gba.gba_gc = &sc->sc_gpio_gc; 97 gba.gba_pins = sc->sc_gpio_pins; 98 gba.gba_npins = GSCGPIO_NPINS; 99 100 sc->sc_gpiobus = config_found_sm_loc(self, "gpiobus", loc, 101 &gba, gpiobus_print, NULL); 102 return 0; 103 } 104 #endif 105 106 return pcibrescan(self, ifattr, loc); 107 } 108 109 int 110 gscpcib_match(device_t parent, cfdata_t match, void *aux) 111 { 112 struct pci_attach_args *pa = aux; 113 114 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 115 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 116 return (0); 117 118 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 119 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SC1100_ISA) 120 return (2); /* supersede pcib(4) */ 121 122 return (0); 123 } 124 125 void 126 gscpcib_attach(device_t parent, device_t self, void *aux) 127 { 128 struct gscpcib_softc *sc = device_private(self); 129 struct pci_attach_args *pa = aux; 130 pcireg_t gpiobase; 131 int i; 132 133 /* Map GPIO I/O space */ 134 gpiobase = pci_conf_read(pa->pa_pc, pa->pa_tag, GSCGPIO_BASE); 135 sc->sc_gpio_iot = pa->pa_iot; 136 if (bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(gpiobase), 137 GSCGPIO_SIZE, 0, &sc->sc_gpio_ioh)) { 138 printf(": failed to map GPIO I/O space"); 139 goto corepcib; 140 } 141 142 /* Initialize pins array */ 143 for (i = 0; i < GSCGPIO_NPINS; i++) { 144 sc->sc_gpio_pins[i].pin_num = i; 145 sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT | 146 GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | 147 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 148 GPIO_PIN_PULLUP; 149 150 /* safe defaults */ 151 sc->sc_gpio_pins[i].pin_flags = GPIO_PIN_TRISTATE; 152 sc->sc_gpio_pins[i].pin_state = GPIO_PIN_LOW; 153 gscpcib_gpio_pin_ctl(sc, i, sc->sc_gpio_pins[i].pin_flags); 154 gscpcib_gpio_pin_write(sc, i, sc->sc_gpio_pins[i].pin_state); 155 } 156 157 /* Create controller tag */ 158 sc->sc_gpio_gc.gp_cookie = sc; 159 sc->sc_gpio_gc.gp_pin_read = gscpcib_gpio_pin_read; 160 sc->sc_gpio_gc.gp_pin_write = gscpcib_gpio_pin_write; 161 sc->sc_gpio_gc.gp_pin_ctl = gscpcib_gpio_pin_ctl; 162 163 sc->sc_gpio_present = true; 164 165 corepcib: 166 /* Provide core pcib(4) functionality */ 167 pcibattach(parent, self, aux); 168 169 gscpcib_rescan(self, "gpiobus", NULL); 170 } 171 172 int 173 gscpcib_detach(device_t self, int flags) 174 { 175 int rc; 176 struct gscpcib_softc *sc = device_private(self); 177 178 if ((rc = config_detach_children(self, flags)) != 0) 179 return rc; 180 181 if ((rc = pcibdetach(self, flags)) != 0) 182 return rc; 183 184 if (sc->sc_gpio_present) 185 bus_space_unmap(sc->sc_gpio_iot, sc->sc_gpio_ioh, GSCGPIO_SIZE); 186 187 return rc; 188 } 189 190 static inline void 191 gscpcib_gpio_pin_select(struct gscpcib_softc *sc, int pin) 192 { 193 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, GSCGPIO_SEL, pin); 194 } 195 196 int 197 gscpcib_gpio_pin_read(void *arg, int pin) 198 { 199 struct gscpcib_softc *sc = arg; 200 int reg, shift; 201 uint32_t data; 202 203 reg = (pin < 32 ? GSCGPIO_GPDI0 : GSCGPIO_GPDI1); 204 shift = pin % 32; 205 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 206 207 return ((data >> shift) & 0x1); 208 } 209 210 void 211 gscpcib_gpio_pin_write(void *arg, int pin, int value) 212 { 213 struct gscpcib_softc *sc = arg; 214 int reg, shift; 215 uint32_t data; 216 217 reg = (pin < 32 ? GSCGPIO_GPDO0 : GSCGPIO_GPDO1); 218 shift = pin % 32; 219 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 220 if (value == 0) 221 data &= ~(1 << shift); 222 else if (value == 1) 223 data |= (1 << shift); 224 225 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 226 } 227 228 void 229 gscpcib_gpio_pin_ctl(void *arg, int pin, int flags) 230 { 231 struct gscpcib_softc *sc = arg; 232 uint32_t conf; 233 234 gscpcib_gpio_pin_select(sc, pin); 235 conf = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 236 GSCGPIO_CONF); 237 238 conf &= ~(GSCGPIO_CONF_OUTPUTEN | GSCGPIO_CONF_PUSHPULL | 239 GSCGPIO_CONF_PULLUP); 240 if ((flags & GPIO_PIN_TRISTATE) == 0) 241 conf |= GSCGPIO_CONF_OUTPUTEN; 242 if (flags & GPIO_PIN_PUSHPULL) 243 conf |= GSCGPIO_CONF_PUSHPULL; 244 if (flags & GPIO_PIN_PULLUP) 245 conf |= GSCGPIO_CONF_PULLUP; 246 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 247 GSCGPIO_CONF, conf); 248 } 249
Indexes created Wed Sep 24 05:09:52 GMT 2025