gscpcib.c revision 1.6
1 /* $NetBSD: gscpcib.c,v 1.6 2006/09/24 03:33:30 jmcneill Exp $ */ 2 /* $OpenBSD: gscpcib.c,v 1.3 2004/10/05 19:02:33 grange Exp $ */ 3 /* 4 * Copyright (c) 2004 Alexander Yurchenko <grange (at) openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Special driver for the National Semiconductor Geode SC1100 PCI-ISA bridge 21 * that attaches instead of pcib(4). In addition to the core pcib(4) 22 * functionality this driver provides support for the GPIO interface. 23 */ 24 25 #include <sys/param.h> 26 #include <sys/systm.h> 27 #include <sys/device.h> 28 #include <sys/gpio.h> 29 #include <sys/kernel.h> 30 31 #include <machine/bus.h> 32 33 #include <dev/pci/pcireg.h> 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 37 #include <dev/gpio/gpiovar.h> 38 39 #include <i386/pci/gscpcibreg.h> 40 41 struct gscpcib_softc { 42 struct device sc_dev; 43 44 /* GPIO interface */ 45 bus_space_tag_t sc_gpio_iot; 46 bus_space_handle_t sc_gpio_ioh; 47 struct gpio_chipset_tag sc_gpio_gc; 48 gpio_pin_t sc_gpio_pins[GSCGPIO_NPINS]; 49 }; 50 51 int gscpcib_match(struct device *, struct cfdata *, void *); 52 void gscpcib_attach(struct device *, struct device *, void *); 53 54 int gscpcib_gpio_pin_read(void *, int); 55 void gscpcib_gpio_pin_write(void *, int, int); 56 void gscpcib_gpio_pin_ctl(void *, int, int); 57 58 /* arch/i386/pci/pcib.c */ 59 void pcibattach(struct device *, struct device *, void *); 60 61 CFATTACH_DECL(gscpcib, sizeof(struct gscpcib_softc), 62 gscpcib_match, gscpcib_attach, NULL, NULL); 63 64 extern struct cfdriver gscpcib_cd; 65 66 int 67 gscpcib_match(struct device *parent, struct cfdata *match, void *aux) 68 { 69 struct pci_attach_args *pa = aux; 70 71 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 72 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 73 return (0); 74 75 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 76 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SC1100_ISA) 77 return (2); /* supersede pcib(4) */ 78 79 return (0); 80 } 81 82 void 83 gscpcib_attach(struct device *parent, struct device *self, void *aux) 84 { 85 struct gscpcib_softc *sc = (struct gscpcib_softc *)self; 86 struct pci_attach_args *pa = aux; 87 struct gpiobus_attach_args gba; 88 pcireg_t gpiobase; 89 int i; 90 int gpio_present = 0; 91 92 /* Map GPIO I/O space */ 93 gpiobase = pci_conf_read(pa->pa_pc, pa->pa_tag, GSCGPIO_BASE); 94 sc->sc_gpio_iot = pa->pa_iot; 95 if (bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(gpiobase), 96 GSCGPIO_SIZE, 0, &sc->sc_gpio_ioh)) { 97 printf(": failed to map GPIO I/O space"); 98 goto corepcib; 99 } 100 101 /* Initialize pins array */ 102 for (i = 0; i < GSCGPIO_NPINS; i++) { 103 sc->sc_gpio_pins[i].pin_num = i; 104 sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT | 105 GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | 106 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 107 GPIO_PIN_PULLUP; 108 109 /* safe defaults */ 110 sc->sc_gpio_pins[i].pin_flags = GPIO_PIN_TRISTATE; 111 sc->sc_gpio_pins[i].pin_state = GPIO_PIN_LOW; 112 gscpcib_gpio_pin_ctl(sc, i, sc->sc_gpio_pins[i].pin_flags); 113 gscpcib_gpio_pin_write(sc, i, sc->sc_gpio_pins[i].pin_state); 114 } 115 116 /* Create controller tag */ 117 sc->sc_gpio_gc.gp_cookie = sc; 118 sc->sc_gpio_gc.gp_pin_read = gscpcib_gpio_pin_read; 119 sc->sc_gpio_gc.gp_pin_write = gscpcib_gpio_pin_write; 120 sc->sc_gpio_gc.gp_pin_ctl = gscpcib_gpio_pin_ctl; 121 122 gba.gba_gc = &sc->sc_gpio_gc; 123 gba.gba_pins = sc->sc_gpio_pins; 124 gba.gba_npins = GSCGPIO_NPINS; 125 126 gpio_present = 1; 127 128 corepcib: 129 /* Provide core pcib(4) functionality */ 130 pcibattach(parent, self, aux); 131 132 /* Attach GPIO framework */ 133 if (gpio_present) 134 config_found_ia(&sc->sc_dev, "gpiobus", &gba, gpiobus_print); 135 } 136 137 static inline void 138 gscpcib_gpio_pin_select(struct gscpcib_softc *sc, int pin) 139 { 140 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, GSCGPIO_SEL, pin); 141 } 142 143 int 144 gscpcib_gpio_pin_read(void *arg, int pin) 145 { 146 struct gscpcib_softc *sc = arg; 147 int reg, shift; 148 uint32_t data; 149 150 reg = (pin < 32 ? GSCGPIO_GPDI0 : GSCGPIO_GPDI1); 151 shift = pin % 32; 152 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 153 154 return ((data >> shift) & 0x1); 155 } 156 157 void 158 gscpcib_gpio_pin_write(void *arg, int pin, int value) 159 { 160 struct gscpcib_softc *sc = arg; 161 int reg, shift; 162 uint32_t data; 163 164 reg = (pin < 32 ? GSCGPIO_GPDO0 : GSCGPIO_GPDO1); 165 shift = pin % 32; 166 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 167 if (value == 0) 168 data &= ~(1 << shift); 169 else if (value == 1) 170 data |= (1 << shift); 171 172 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 173 } 174 175 void 176 gscpcib_gpio_pin_ctl(void *arg, int pin, int flags) 177 { 178 struct gscpcib_softc *sc = arg; 179 uint32_t conf; 180 181 gscpcib_gpio_pin_select(sc, pin); 182 conf = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 183 GSCGPIO_CONF); 184 185 conf &= ~(GSCGPIO_CONF_OUTPUTEN | GSCGPIO_CONF_PUSHPULL | 186 GSCGPIO_CONF_PULLUP); 187 if ((flags & GPIO_PIN_TRISTATE) == 0) 188 conf |= GSCGPIO_CONF_OUTPUTEN; 189 if (flags & GPIO_PIN_PUSHPULL) 190 conf |= GSCGPIO_CONF_PUSHPULL; 191 if (flags & GPIO_PIN_PULLUP) 192 conf |= GSCGPIO_CONF_PULLUP; 193 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 194 GSCGPIO_CONF, conf); 195 } 196
Indexes created Tue Oct 14 21:09:58 GMT 2025