gscpcib.c revision 1.8
1 /* $NetBSD: gscpcib.c,v 1.8 2006/11/16 01:32:39 christos Exp $ */ 2 /* $OpenBSD: gscpcib.c,v 1.3 2004/10/05 19:02:33 grange Exp $ */ 3 /* 4 * Copyright (c) 2004 Alexander Yurchenko <grange (at) openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Special driver for the National Semiconductor Geode SC1100 PCI-ISA bridge 21 * that attaches instead of pcib(4). In addition to the core pcib(4) 22 * functionality this driver provides support for the GPIO interface. 23 */ 24 25 #include <sys/param.h> 26 #include <sys/systm.h> 27 #include <sys/device.h> 28 #include <sys/gpio.h> 29 #include <sys/kernel.h> 30 31 #include <machine/bus.h> 32 33 #include <dev/pci/pcireg.h> 34 #include <dev/pci/pcivar.h> 35 #include <dev/pci/pcidevs.h> 36 37 #include <dev/gpio/gpiovar.h> 38 39 #include <i386/pci/gscpcibreg.h> 40 41 struct gscpcib_softc { 42 struct device sc_dev; 43 44 /* GPIO interface */ 45 bus_space_tag_t sc_gpio_iot; 46 bus_space_handle_t sc_gpio_ioh; 47 struct gpio_chipset_tag sc_gpio_gc; 48 gpio_pin_t sc_gpio_pins[GSCGPIO_NPINS]; 49 }; 50 51 int gscpcib_match(struct device *, struct cfdata *, void *); 52 void gscpcib_attach(struct device *, struct device *, void *); 53 54 int gscpcib_gpio_pin_read(void *, int); 55 void gscpcib_gpio_pin_write(void *, int, int); 56 void gscpcib_gpio_pin_ctl(void *, int, int); 57 58 /* arch/i386/pci/pcib.c */ 59 void pcibattach(struct device *, struct device *, void *); 60 61 CFATTACH_DECL(gscpcib, sizeof(struct gscpcib_softc), 62 gscpcib_match, gscpcib_attach, NULL, NULL); 63 64 extern struct cfdriver gscpcib_cd; 65 66 int 67 gscpcib_match(struct device *parent, struct cfdata *match, 68 void *aux) 69 { 70 struct pci_attach_args *pa = aux; 71 72 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 73 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA) 74 return (0); 75 76 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 77 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SC1100_ISA) 78 return (2); /* supersede pcib(4) */ 79 80 return (0); 81 } 82 83 void 84 gscpcib_attach(struct device *parent, struct device *self, void *aux) 85 { 86 struct gscpcib_softc *sc = (struct gscpcib_softc *)self; 87 struct pci_attach_args *pa = aux; 88 struct gpiobus_attach_args gba; 89 pcireg_t gpiobase; 90 int i; 91 int gpio_present = 0; 92 93 /* Map GPIO I/O space */ 94 gpiobase = pci_conf_read(pa->pa_pc, pa->pa_tag, GSCGPIO_BASE); 95 sc->sc_gpio_iot = pa->pa_iot; 96 if (bus_space_map(sc->sc_gpio_iot, PCI_MAPREG_IO_ADDR(gpiobase), 97 GSCGPIO_SIZE, 0, &sc->sc_gpio_ioh)) { 98 printf(": failed to map GPIO I/O space"); 99 goto corepcib; 100 } 101 102 /* Initialize pins array */ 103 for (i = 0; i < GSCGPIO_NPINS; i++) { 104 sc->sc_gpio_pins[i].pin_num = i; 105 sc->sc_gpio_pins[i].pin_caps = GPIO_PIN_INPUT | 106 GPIO_PIN_OUTPUT | GPIO_PIN_OPENDRAIN | 107 GPIO_PIN_PUSHPULL | GPIO_PIN_TRISTATE | 108 GPIO_PIN_PULLUP; 109 110 /* safe defaults */ 111 sc->sc_gpio_pins[i].pin_flags = GPIO_PIN_TRISTATE; 112 sc->sc_gpio_pins[i].pin_state = GPIO_PIN_LOW; 113 gscpcib_gpio_pin_ctl(sc, i, sc->sc_gpio_pins[i].pin_flags); 114 gscpcib_gpio_pin_write(sc, i, sc->sc_gpio_pins[i].pin_state); 115 } 116 117 /* Create controller tag */ 118 sc->sc_gpio_gc.gp_cookie = sc; 119 sc->sc_gpio_gc.gp_pin_read = gscpcib_gpio_pin_read; 120 sc->sc_gpio_gc.gp_pin_write = gscpcib_gpio_pin_write; 121 sc->sc_gpio_gc.gp_pin_ctl = gscpcib_gpio_pin_ctl; 122 123 gba.gba_gc = &sc->sc_gpio_gc; 124 gba.gba_pins = sc->sc_gpio_pins; 125 gba.gba_npins = GSCGPIO_NPINS; 126 127 gpio_present = 1; 128 129 corepcib: 130 /* Provide core pcib(4) functionality */ 131 pcibattach(parent, self, aux); 132 133 /* Attach GPIO framework */ 134 if (gpio_present) 135 config_found_ia(&sc->sc_dev, "gpiobus", &gba, gpiobus_print); 136 } 137 138 static inline void 139 gscpcib_gpio_pin_select(struct gscpcib_softc *sc, int pin) 140 { 141 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, GSCGPIO_SEL, pin); 142 } 143 144 int 145 gscpcib_gpio_pin_read(void *arg, int pin) 146 { 147 struct gscpcib_softc *sc = arg; 148 int reg, shift; 149 uint32_t data; 150 151 reg = (pin < 32 ? GSCGPIO_GPDI0 : GSCGPIO_GPDI1); 152 shift = pin % 32; 153 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 154 155 return ((data >> shift) & 0x1); 156 } 157 158 void 159 gscpcib_gpio_pin_write(void *arg, int pin, int value) 160 { 161 struct gscpcib_softc *sc = arg; 162 int reg, shift; 163 uint32_t data; 164 165 reg = (pin < 32 ? GSCGPIO_GPDO0 : GSCGPIO_GPDO1); 166 shift = pin % 32; 167 data = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg); 168 if (value == 0) 169 data &= ~(1 << shift); 170 else if (value == 1) 171 data |= (1 << shift); 172 173 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, reg, data); 174 } 175 176 void 177 gscpcib_gpio_pin_ctl(void *arg, int pin, int flags) 178 { 179 struct gscpcib_softc *sc = arg; 180 uint32_t conf; 181 182 gscpcib_gpio_pin_select(sc, pin); 183 conf = bus_space_read_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 184 GSCGPIO_CONF); 185 186 conf &= ~(GSCGPIO_CONF_OUTPUTEN | GSCGPIO_CONF_PUSHPULL | 187 GSCGPIO_CONF_PULLUP); 188 if ((flags & GPIO_PIN_TRISTATE) == 0) 189 conf |= GSCGPIO_CONF_OUTPUTEN; 190 if (flags & GPIO_PIN_PUSHPULL) 191 conf |= GSCGPIO_CONF_PUSHPULL; 192 if (flags & GPIO_PIN_PULLUP) 193 conf |= GSCGPIO_CONF_PULLUP; 194 bus_space_write_4(sc->sc_gpio_iot, sc->sc_gpio_ioh, 195 GSCGPIO_CONF, conf); 196 } 197
Indexes created Fri Sep 26 20:09:58 GMT 2025