1 /* $NetBSD: opti82c558.c,v 1.10 2011/07/01 17:37:26 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1999, by UCHIYAMA Yasushi 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. The name of the developer may NOT be used to endorse or promote products 43 * derived from this software without specific prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 46 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 49 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 50 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 51 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 52 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 53 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 54 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 55 * SUCH DAMAGE. 56 */ 57 58 /* 59 * Support for the Opti 82c558 PCI-ISA bridge interrupt controller. 60 */ 61 62 #include <sys/cdefs.h> 63 __KERNEL_RCSID(0, "$NetBSD: opti82c558.c,v 1.10 2011/07/01 17:37:26 dyoung Exp $"); 64 65 #include <sys/param.h> 66 #include <sys/systm.h> 67 #include <sys/device.h> 68 #include <sys/malloc.h> 69 70 #include <machine/intr.h> 71 #include <sys/bus.h> 72 73 #include <dev/pci/pcivar.h> 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcidevs.h> 76 77 #include <i386/pci/pci_intr_fixup.h> 78 #include <i386/pci/opti82c558reg.h> 79 80 int opti82c558_getclink(pciintr_icu_handle_t, int, int *); 81 int opti82c558_get_intr(pciintr_icu_handle_t, int, int *); 82 int opti82c558_set_intr(pciintr_icu_handle_t, int, int); 83 int opti82c558_get_trigger(pciintr_icu_handle_t, int, int *); 84 int opti82c558_set_trigger(pciintr_icu_handle_t, int, int); 85 86 const struct pciintr_icu opti82c558_pci_icu = { 87 opti82c558_getclink, 88 opti82c558_get_intr, 89 opti82c558_set_intr, 90 opti82c558_get_trigger, 91 opti82c558_set_trigger, 92 }; 93 94 struct opti82c558_handle { 95 pci_chipset_tag_t ph_pc; 96 pcitag_t ph_tag; 97 }; 98 99 static const int viper_pirq_decode[] = { 100 -1, 5, 9, 10, 11, 12, 14, 15 101 }; 102 103 static const int viper_pirq_encode[] = { 104 -1, /* 0 */ 105 -1, /* 1 */ 106 -1, /* 2 */ 107 -1, /* 3 */ 108 -1, /* 4 */ 109 VIPER_PIRQ_5, /* 5 */ 110 -1, /* 6 */ 111 -1, /* 7 */ 112 -1, /* 8 */ 113 VIPER_PIRQ_9, /* 9 */ 114 VIPER_PIRQ_10, /* 10 */ 115 VIPER_PIRQ_11, /* 11 */ 116 VIPER_PIRQ_12, /* 12 */ 117 -1, /* 13 */ 118 VIPER_PIRQ_14, /* 14 */ 119 VIPER_PIRQ_15, /* 15 */ 120 }; 121 122 int 123 opti82c558_init(pci_chipset_tag_t pc, bus_space_tag_t iot, 124 pcitag_t tag, pciintr_icu_tag_t *ptagp, pciintr_icu_handle_t *phandp) 125 { 126 struct opti82c558_handle *ph; 127 128 ph = malloc(sizeof(*ph), M_DEVBUF, M_NOWAIT); 129 if (ph == NULL) 130 return (1); 131 132 ph->ph_pc = pc; 133 ph->ph_tag = tag; 134 135 *ptagp = &opti82c558_pci_icu; 136 *phandp = ph; 137 return (0); 138 } 139 140 int 141 opti82c558_getclink(pciintr_icu_handle_t v, int link, int *clinkp) 142 { 143 144 if (VIPER_LEGAL_LINK(link - 1)) { 145 *clinkp = link - 1; 146 return (0); 147 } 148 149 return (1); 150 } 151 152 int 153 opti82c558_get_intr(pciintr_icu_handle_t v, int clink, int *irqp) 154 { 155 struct opti82c558_handle *ph = v; 156 pcireg_t reg; 157 int val; 158 159 if (VIPER_LEGAL_LINK(clink) == 0) 160 return (1); 161 162 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); 163 val = VIPER_PIRQ(reg, clink); 164 *irqp = (val == VIPER_PIRQ_NONE) ? 165 X86_PCI_INTERRUPT_LINE_NO_CONNECTION : viper_pirq_decode[val]; 166 167 return (0); 168 } 169 170 int 171 opti82c558_set_intr(pciintr_icu_handle_t v, int clink, int irq) 172 { 173 struct opti82c558_handle *ph = v; 174 int shift; 175 pcireg_t reg; 176 177 if (VIPER_LEGAL_LINK(clink) == 0 || VIPER_LEGAL_IRQ(irq) == 0) 178 return (1); 179 180 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); 181 shift = VIPER_PIRQ_SELECT_SHIFT * clink; 182 reg &= ~(VIPER_PIRQ_SELECT_MASK << shift); 183 reg |= (viper_pirq_encode[irq] << shift); 184 pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg); 185 186 return (0); 187 } 188 189 int 190 opti82c558_get_trigger(pciintr_icu_handle_t v, int irq, int *triggerp) 191 { 192 struct opti82c558_handle *ph = v; 193 pcireg_t reg; 194 195 if (VIPER_LEGAL_IRQ(irq) == 0) { 196 /* ISA IRQ? */ 197 *triggerp = IST_EDGE; 198 return (0); 199 } 200 201 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); 202 if ((reg >> (VIPER_CFG_TRIGGER_SHIFT + viper_pirq_encode[irq])) & 1) 203 *triggerp = IST_LEVEL; 204 else 205 *triggerp = IST_EDGE; 206 207 return (0); 208 } 209 210 int 211 opti82c558_set_trigger(pciintr_icu_handle_t v, int irq, int trigger) 212 { 213 struct opti82c558_handle *ph = v; 214 int shift; 215 pcireg_t reg; 216 217 if (VIPER_LEGAL_IRQ(irq) == 0) { 218 /* ISA IRQ? */ 219 return ((trigger != IST_LEVEL) ? 0 : 1); 220 } 221 222 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ); 223 shift = (VIPER_CFG_TRIGGER_SHIFT + viper_pirq_encode[irq]); 224 if (trigger == IST_LEVEL) 225 reg |= (1 << shift); 226 else 227 reg &= ~(1 << shift); 228 pci_conf_write(ph->ph_pc, ph->ph_tag, VIPER_CFG_PIRQ, reg); 229 230 return (0); 231 } 232
Indexes created Tue Sep 23 14:10:03 GMT 2025