1 /* $NetBSD: piixpcib.c,v 1.24 2019/10/18 15:00:15 hannken Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2006 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto, Matthew R. Green, and Jared D. McNeill. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel PIIX4 PCI-ISA bridge device driver with CPU frequency scaling support 34 * 35 * Based on the FreeBSD 'smist' cpufreq driver by Bruno Ducrot 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: piixpcib.c,v 1.24 2019/10/18 15:00:15 hannken Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/sysctl.h> 46 #include <sys/bus.h> 47 48 #include <machine/frame.h> 49 #include <machine/bioscall.h> 50 #include <machine/bootinfo.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcidevs.h> 55 56 #include <i386/pci/piixreg.h> 57 #include <x86/pci/pcibvar.h> 58 59 #define PIIX4_PIRQRC 0x60 60 61 struct piixpcib_softc { 62 /* we call pcibattach() which assumes our softc starts like this: */ 63 64 struct pcib_softc sc_pcib; 65 66 device_t sc_dev; 67 68 int sc_smi_cmd; 69 int sc_smi_data; 70 int sc_command; 71 int sc_flags; 72 73 bus_space_tag_t sc_iot; 74 bus_space_handle_t sc_ioh; 75 76 pcireg_t sc_pirqrc; 77 uint8_t sc_elcr[2]; 78 }; 79 80 static int piixpcibmatch(device_t, cfdata_t, void *); 81 static void piixpcibattach(device_t, device_t, void *); 82 83 static bool piixpcib_suspend(device_t, const pmf_qual_t *); 84 static bool piixpcib_resume(device_t, const pmf_qual_t *); 85 86 static void speedstep_configure(struct piixpcib_softc *, 87 const struct pci_attach_args *); 88 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 89 90 static struct piixpcib_softc *speedstep_cookie; /* XXX */ 91 92 CFATTACH_DECL_NEW(piixpcib, sizeof(struct piixpcib_softc), 93 piixpcibmatch, piixpcibattach, NULL, NULL); 94 95 /* 96 * Autoconf callbacks. 97 */ 98 static int 99 piixpcibmatch(device_t parent, cfdata_t match, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 103 /* We are ISA bridge, of course */ 104 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 105 (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA && 106 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_MISC)) { 107 return 0; 108 } 109 110 /* Matches only Intel PIIX4 */ 111 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 112 switch (PCI_PRODUCT(pa->pa_id)) { 113 case PCI_PRODUCT_INTEL_82371AB_ISA: /* PIIX4 */ 114 case PCI_PRODUCT_INTEL_82440MX_PMC: /* PIIX4 in MX440 */ 115 return 10; 116 } 117 } 118 119 return 0; 120 } 121 122 static void 123 piixpcibattach(device_t parent, device_t self, void *aux) 124 { 125 struct pci_attach_args *pa = aux; 126 struct piixpcib_softc *sc = device_private(self); 127 128 sc->sc_dev = self; 129 sc->sc_iot = pa->pa_iot; 130 131 pcibattach(parent, self, aux); 132 133 /* Set up SpeedStep. */ 134 speedstep_configure(sc, pa); 135 136 /* Map edge/level control registers */ 137 if (bus_space_map(sc->sc_iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, 138 &sc->sc_ioh)) { 139 aprint_error_dev(self, 140 "can't map edge/level control registers\n"); 141 return; 142 } 143 144 if (!pmf_device_register(self, piixpcib_suspend, piixpcib_resume)) 145 aprint_error_dev(self, "couldn't establish power handler\n"); 146 } 147 148 static bool 149 piixpcib_suspend(device_t dv, const pmf_qual_t *qual) 150 { 151 struct piixpcib_softc *sc = device_private(dv); 152 153 /* capture PIRQX route control registers */ 154 sc->sc_pirqrc = pci_conf_read(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, 155 PIIX4_PIRQRC); 156 157 /* capture edge/level control registers */ 158 sc->sc_elcr[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0); 159 sc->sc_elcr[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 1); 160 161 return true; 162 } 163 164 static bool 165 piixpcib_resume(device_t dv, const pmf_qual_t *qual) 166 { 167 struct piixpcib_softc *sc = device_private(dv); 168 169 /* restore PIRQX route control registers */ 170 pci_conf_write(sc->sc_pcib.sc_pc, sc->sc_pcib.sc_tag, PIIX4_PIRQRC, 171 sc->sc_pirqrc); 172 173 /* restore edge/level control registers */ 174 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, sc->sc_elcr[0]); 175 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1, sc->sc_elcr[1]); 176 177 return true; 178 } 179 180 /* 181 * Intel PIIX4 (SMI) SpeedStep support. 182 */ 183 184 #define PIIXPCIB_GSIC 0x47534943 185 #define PIIXPCIB_GETOWNER 0 186 #define PIIXPCIB_GETSTATE 1 187 #define PIIXPCIB_SETSTATE 2 188 #define PIIXPCIB_GETFREQS 4 189 190 #define PIIXPCIB_SPEEDSTEP_HIGH 0 191 #define PIIXPCIB_SPEEDSTEP_LOW 1 192 193 static void 194 piixpcib_int15_gsic_call(int *sig, int *smicmd, int *cmd, int *smidata, 195 int *flags) 196 { 197 struct bioscallregs regs; 198 199 /* No bioscall with EFI */ 200 if (lookup_bootinfo(BTINFO_EFI) != NULL) { 201 *sig = *smicmd = *cmd = *smidata = *flags = -1; 202 return; 203 } 204 205 memset(®s, 0, sizeof(struct bioscallregs)); 206 regs.EAX = 0x0000e980; /* IST support */ 207 regs.EDX = PIIXPCIB_GSIC; 208 bioscall(0x15, ®s); 209 210 if (regs.EAX == PIIXPCIB_GSIC) { 211 *sig = regs.EAX; 212 *smicmd = regs.EBX & 0xff; 213 *cmd = (regs.EBX >> 16) & 0xff; 214 *smidata = regs.ECX; 215 *flags = regs.EDX; 216 } else 217 *sig = *smicmd = *cmd = *smidata = *flags = -1; 218 219 return; 220 } 221 222 static int 223 piixpcib_set_ownership(struct piixpcib_softc *sc) 224 { 225 int rv; 226 u_long pmagic; 227 static char magic[] = "Copyright (c) 1999 Intel Corporation"; 228 229 pmagic = vtophys((vaddr_t)magic); 230 231 __asm__ __volatile__( 232 "movl $0, %%edi\n\t" 233 "out %%al, (%%dx)\n" 234 : "=D" (rv) 235 : "a" (sc->sc_command), 236 "b" (0), 237 "c" (0), 238 "d" (sc->sc_smi_cmd), 239 "S" (pmagic) 240 ); 241 242 return (rv ? ENXIO : 0); 243 } 244 245 static int 246 piixpcib_getset_state(struct piixpcib_softc *sc, int *state, int function) 247 { 248 int new; 249 int rv; 250 int eax; 251 252 #ifdef DIAGNOSTIC 253 if (function != PIIXPCIB_GETSTATE && 254 function != PIIXPCIB_SETSTATE) { 255 aprint_error_dev(sc->sc_dev, 256 "GSI called with invalid function %d\n", function); 257 return EINVAL; 258 } 259 #endif 260 261 __asm__ __volatile__( 262 "movl $0, %%edi\n\t" 263 "out %%al, (%%dx)\n" 264 : "=a" (eax), 265 "=b" (new), 266 "=D" (rv) 267 : "a" (sc->sc_command), 268 "b" (function), 269 "c" (*state), 270 "d" (sc->sc_smi_cmd), 271 "S" (0) 272 ); 273 274 *state = new & 1; 275 276 switch (function) { 277 case PIIXPCIB_GETSTATE: 278 if (eax) 279 return ENXIO; 280 break; 281 case PIIXPCIB_SETSTATE: 282 if (rv) 283 return ENXIO; 284 break; 285 } 286 287 return 0; 288 } 289 290 static int 291 piixpcib_get(struct piixpcib_softc *sc) 292 { 293 int rv; 294 int state; 295 296 state = 0; /* XXX gcc */ 297 298 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_GETSTATE); 299 if (rv) 300 return rv; 301 302 return state & 1; 303 } 304 305 static int 306 piixpcib_set(struct piixpcib_softc *sc, int state) 307 { 308 int rv, s; 309 int try; 310 311 if (state != PIIXPCIB_SPEEDSTEP_HIGH && 312 state != PIIXPCIB_SPEEDSTEP_LOW) 313 return ENXIO; 314 if (piixpcib_get(sc) == state) 315 return 0; 316 317 try = 5; 318 319 s = splhigh(); 320 321 do { 322 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_SETSTATE); 323 if (rv) 324 delay(200); 325 } while (rv && --try); 326 327 splx(s); 328 329 return rv; 330 } 331 332 static void 333 speedstep_configure(struct piixpcib_softc *sc, 334 const struct pci_attach_args *pa) 335 { 336 const struct sysctlnode *node, *ssnode; 337 int sig, smicmd, cmd, smidata, flags; 338 int rv; 339 340 piixpcib_int15_gsic_call(&sig, &smicmd, &cmd, &smidata, &flags); 341 342 if (sig != -1) { 343 sc->sc_smi_cmd = smicmd; 344 sc->sc_smi_data = smidata; 345 if (cmd == 0x80) { 346 aprint_debug_dev(sc->sc_dev, 347 "GSIC returned cmd 0x80, should be 0x82\n"); 348 cmd = 0x82; 349 } 350 sc->sc_command = (sig & 0xffffff00) | (cmd & 0xff); 351 sc->sc_flags = flags; 352 } else { 353 /* setup some defaults */ 354 sc->sc_smi_cmd = 0xb2; 355 sc->sc_smi_data = 0xb3; 356 sc->sc_command = 0x47534982; 357 sc->sc_flags = 0; 358 } 359 360 if (piixpcib_set_ownership(sc) != 0) { 361 aprint_error_dev(sc->sc_dev, 362 "unable to claim ownership from the BIOS\n"); 363 return; /* If we can't claim ownership from the BIOS, bail */ 364 } 365 366 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 367 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 368 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 369 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 370 goto err; 371 372 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 373 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 374 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 375 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 376 CTL_EOL)) != 0) 377 goto err; 378 379 /* XXX save the sc for IO tag/handle */ 380 speedstep_cookie = sc; 381 382 aprint_verbose_dev(sc->sc_dev, "SpeedStep SMI enabled\n"); 383 return; 384 385 err: 386 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 387 } 388 389 /* 390 * get/set the SpeedStep state: 0 == low power, 1 == high power. 391 */ 392 static int 393 speedstep_sysctl_helper(SYSCTLFN_ARGS) 394 { 395 struct sysctlnode node; 396 struct piixpcib_softc *sc; 397 uint8_t state, state2; 398 int ostate, nstate, error; 399 400 sc = speedstep_cookie; 401 error = 0; 402 403 state = piixpcib_get(sc); 404 if (state == PIIXPCIB_SPEEDSTEP_HIGH) 405 ostate = 1; 406 else 407 ostate = 0; 408 nstate = ostate; 409 410 node = *rnode; 411 node.sysctl_data = &nstate; 412 413 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 414 if (error || newp == NULL) 415 goto out; 416 417 /* Only two states are available */ 418 if (nstate != 0 && nstate != 1) { 419 error = EINVAL; 420 goto out; 421 } 422 423 state2 = piixpcib_get(sc); 424 if (state2 == PIIXPCIB_SPEEDSTEP_HIGH) 425 ostate = 1; 426 else 427 ostate = 0; 428 429 if (ostate != nstate) 430 { 431 if (nstate == 0) 432 state2 = PIIXPCIB_SPEEDSTEP_LOW; 433 else 434 state2 = PIIXPCIB_SPEEDSTEP_HIGH; 435 436 error = piixpcib_set(sc, state2); 437 } 438 out: 439 return (error); 440 } 441
Indexes created Sat Sep 20 22:09:52 GMT 2025