piixpcib.c revision 1.15
1 /* $NetBSD: piixpcib.c,v 1.15 2008/05/05 11:49:40 xtraeme Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2006 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto, Matthew R. Green, and Jared D. McNeill. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel PIIX4 PCI-ISA bridge device driver with CPU frequency scaling support 34 * 35 * Based on the FreeBSD 'smist' cpufreq driver by Bruno Ducrot 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: piixpcib.c,v 1.15 2008/05/05 11:49:40 xtraeme Exp $"); 40 41 #include <sys/types.h> 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <sys/sysctl.h> 46 #include <machine/bus.h> 47 48 #include <machine/frame.h> 49 #include <machine/bioscall.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <dev/pci/pcireg.h> 53 #include <dev/pci/pcidevs.h> 54 55 #include <i386/pci/piixreg.h> 56 57 #define PIIX4_PIRQRC 0x60 58 59 struct piixpcib_softc { 60 device_t sc_dev; 61 62 pci_chipset_tag_t sc_pc; 63 pcitag_t sc_pcitag; 64 65 int sc_smi_cmd; 66 int sc_smi_data; 67 int sc_command; 68 int sc_flags; 69 70 bus_space_tag_t sc_iot; 71 bus_space_handle_t sc_ioh; 72 73 pcireg_t sc_pirqrc; 74 uint8_t sc_elcr[2]; 75 }; 76 77 static int piixpcibmatch(device_t, cfdata_t, void *); 78 static void piixpcibattach(device_t, device_t, void *); 79 80 static bool piixpcib_suspend(device_t PMF_FN_PROTO); 81 static bool piixpcib_resume(device_t PMF_FN_PROTO); 82 83 static void speedstep_configure(struct piixpcib_softc *, 84 struct pci_attach_args *); 85 static int speedstep_sysctl_helper(SYSCTLFN_ARGS); 86 87 struct piixpcib_softc *speedstep_cookie; /* XXX */ 88 89 /* Defined in arch/i386/pci/pcib.c. */ 90 extern void pcibattach(device_t, device_t, void *); 91 92 CFATTACH_DECL_NEW(piixpcib, sizeof(struct piixpcib_softc), 93 piixpcibmatch, piixpcibattach, NULL, NULL); 94 95 /* 96 * Autoconf callbacks. 97 */ 98 static int 99 piixpcibmatch(device_t parent, cfdata_t match, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 103 /* We are ISA bridge, of course */ 104 if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE || 105 (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA && 106 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_MISC)) { 107 return 0; 108 } 109 110 /* Matches only Intel PIIX4 */ 111 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) { 112 switch (PCI_PRODUCT(pa->pa_id)) { 113 case PCI_PRODUCT_INTEL_82371AB_ISA: /* PIIX4 */ 114 case PCI_PRODUCT_INTEL_82440MX_PMC: /* PIIX4 in MX440 */ 115 return 10; 116 } 117 } 118 119 return 0; 120 } 121 122 static void 123 piixpcibattach(device_t parent, device_t self, void *aux) 124 { 125 struct pci_attach_args *pa = aux; 126 struct piixpcib_softc *sc = device_private(self); 127 128 sc->sc_dev = self; 129 sc->sc_pc = pa->pa_pc; 130 sc->sc_pcitag = pa->pa_tag; 131 sc->sc_iot = pa->pa_iot; 132 133 pcibattach(parent, self, aux); 134 135 /* Set up SpeedStep. */ 136 speedstep_configure(sc, pa); 137 138 /* Map edge/level control registers */ 139 if (bus_space_map(sc->sc_iot, PIIX_REG_ELCR, PIIX_REG_ELCR_SIZE, 0, 140 &sc->sc_ioh)) { 141 aprint_error_dev(self, "can't map edge/level control registers\n"); 142 return; 143 } 144 145 if (!pmf_device_register(self, piixpcib_suspend, piixpcib_resume)) 146 aprint_error_dev(self, "couldn't establish power handler\n"); 147 } 148 149 static bool 150 piixpcib_suspend(device_t dv PMF_FN_ARGS) 151 { 152 struct piixpcib_softc *sc = device_private(dv); 153 154 /* capture PIRQX route control registers */ 155 sc->sc_pirqrc = pci_conf_read(sc->sc_pc, sc->sc_pcitag, PIIX4_PIRQRC); 156 157 /* capture edge/level control registers */ 158 sc->sc_elcr[0] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 0); 159 sc->sc_elcr[1] = bus_space_read_1(sc->sc_iot, sc->sc_ioh, 1); 160 161 return true; 162 } 163 164 static bool 165 piixpcib_resume(device_t dv PMF_FN_ARGS) 166 { 167 struct piixpcib_softc *sc = device_private(dv); 168 169 /* restore PIRQX route control registers */ 170 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PIIX4_PIRQRC, sc->sc_pirqrc); 171 172 /* restore edge/level control registers */ 173 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 0, sc->sc_elcr[0]); 174 bus_space_write_1(sc->sc_iot, sc->sc_ioh, 1, sc->sc_elcr[1]); 175 176 return true; 177 } 178 179 /* 180 * Intel PIIX4 (SMI) SpeedStep support. 181 */ 182 183 #define PIIXPCIB_GSIC 0x47534943 184 #define PIIXPCIB_GETOWNER 0 185 #define PIIXPCIB_GETSTATE 1 186 #define PIIXPCIB_SETSTATE 2 187 #define PIIXPCIB_GETFREQS 4 188 189 #define PIIXPCIB_SPEEDSTEP_HIGH 0 190 #define PIIXPCIB_SPEEDSTEP_LOW 1 191 192 static void 193 piixpcib_int15_gsic_call(int *sig, int *smicmd, int *cmd, int *smidata, int *flags) 194 { 195 struct bioscallregs regs; 196 197 memset(®s, 0, sizeof(struct bioscallregs)); 198 regs.EAX = 0x0000e980; /* IST support */ 199 regs.EDX = PIIXPCIB_GSIC; 200 bioscall(0x15, ®s); 201 202 if (regs.EAX == PIIXPCIB_GSIC) { 203 *sig = regs.EAX; 204 *smicmd = regs.EBX & 0xff; 205 *cmd = (regs.EBX >> 16) & 0xff; 206 *smidata = regs.ECX; 207 *flags = regs.EDX; 208 } else 209 *sig = *smicmd = *cmd = *smidata = *flags = -1; 210 211 return; 212 } 213 214 static int 215 piixpcib_set_ownership(struct piixpcib_softc *sc) 216 { 217 int rv; 218 paddr_t pmagic; 219 static char magic[] = "Copyright (c) 1999 Intel Corporation"; 220 221 pmagic = vtophys((vaddr_t)magic); 222 223 __asm__ __volatile__( 224 "movl $0, %%edi\n\t" 225 "out %%al, (%%dx)\n" 226 : "=D" (rv) 227 : "a" (sc->sc_command), 228 "b" (0), 229 "c" (0), 230 "d" (sc->sc_smi_cmd), 231 "S" (pmagic) 232 ); 233 234 return (rv ? ENXIO : 0); 235 } 236 237 static int 238 piixpcib_getset_state(struct piixpcib_softc *sc, int *state, int function) 239 { 240 int new; 241 int rv; 242 int eax; 243 244 #ifdef DIAGNOSTIC 245 if (function != PIIXPCIB_GETSTATE && 246 function != PIIXPCIB_SETSTATE) { 247 aprint_error_dev(sc->sc_dev, "GSI called with invalid function %d\n", 248 function); 249 return EINVAL; 250 } 251 #endif 252 253 __asm__ __volatile__( 254 "movl $0, %%edi\n\t" 255 "out %%al, (%%dx)\n" 256 : "=a" (eax), 257 "=b" (new), 258 "=D" (rv) 259 : "a" (sc->sc_command), 260 "b" (function), 261 "c" (*state), 262 "d" (sc->sc_smi_cmd), 263 "S" (0) 264 ); 265 266 *state = new & 1; 267 268 switch (function) { 269 case PIIXPCIB_GETSTATE: 270 if (eax) 271 return ENXIO; 272 break; 273 case PIIXPCIB_SETSTATE: 274 if (rv) 275 return ENXIO; 276 break; 277 } 278 279 return 0; 280 } 281 282 static int 283 piixpcib_get(struct piixpcib_softc *sc) 284 { 285 int rv; 286 int state; 287 288 state = 0; /* XXX gcc */ 289 290 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_GETSTATE); 291 if (rv) 292 return rv; 293 294 return state & 1; 295 } 296 297 static int 298 piixpcib_set(struct piixpcib_softc *sc, int state) 299 { 300 int rv, s; 301 int try; 302 303 if (state != PIIXPCIB_SPEEDSTEP_HIGH && 304 state != PIIXPCIB_SPEEDSTEP_LOW) 305 return ENXIO; 306 if (piixpcib_get(sc) == state) 307 return 0; 308 309 try = 5; 310 311 s = splhigh(); 312 313 do { 314 rv = piixpcib_getset_state(sc, &state, PIIXPCIB_SETSTATE); 315 if (rv) 316 delay(200); 317 } while (rv && --try); 318 319 splx(s); 320 321 return rv; 322 } 323 324 static void 325 speedstep_configure(struct piixpcib_softc *sc, 326 struct pci_attach_args *pa) 327 { 328 const struct sysctlnode *node, *ssnode; 329 int sig, smicmd, cmd, smidata, flags; 330 int rv; 331 332 piixpcib_int15_gsic_call(&sig, &smicmd, &cmd, &smidata, &flags); 333 334 if (sig != -1) { 335 sc->sc_smi_cmd = smicmd; 336 sc->sc_smi_data = smidata; 337 if (cmd == 0x80) { 338 aprint_debug_dev(sc->sc_dev, "GSIC returned cmd 0x80, should be 0x82\n"); 339 cmd = 0x82; 340 } 341 sc->sc_command = (sig & 0xffffff00) | (cmd & 0xff); 342 sc->sc_flags = flags; 343 } else { 344 /* setup some defaults */ 345 sc->sc_smi_cmd = 0xb2; 346 sc->sc_smi_data = 0xb3; 347 sc->sc_command = 0x47534982; 348 sc->sc_flags = 0; 349 } 350 351 if (piixpcib_set_ownership(sc) != 0) { 352 aprint_error_dev(sc->sc_dev, "unable to claim ownership from the BIOS\n"); 353 return; /* If we can't claim ownership from the BIOS, bail */ 354 } 355 356 /* Put in machdep.speedstep_state (0 for low, 1 for high). */ 357 if ((rv = sysctl_createv(NULL, 0, NULL, &node, 358 CTLFLAG_PERMANENT, CTLTYPE_NODE, "machdep", NULL, 359 NULL, 0, NULL, 0, CTL_MACHDEP, CTL_EOL)) != 0) 360 goto err; 361 362 /* CTLFLAG_ANYWRITE? kernel option like EST? */ 363 if ((rv = sysctl_createv(NULL, 0, &node, &ssnode, 364 CTLFLAG_READWRITE, CTLTYPE_INT, "speedstep_state", NULL, 365 speedstep_sysctl_helper, 0, NULL, 0, CTL_CREATE, 366 CTL_EOL)) != 0) 367 goto err; 368 369 /* XXX save the sc for IO tag/handle */ 370 speedstep_cookie = sc; 371 372 aprint_verbose_dev(sc->sc_dev, "SpeedStep SMI enabled\n"); 373 return; 374 375 err: 376 aprint_normal("%s: sysctl_createv failed (rv = %d)\n", __func__, rv); 377 } 378 379 /* 380 * get/set the SpeedStep state: 0 == low power, 1 == high power. 381 */ 382 static int 383 speedstep_sysctl_helper(SYSCTLFN_ARGS) 384 { 385 struct sysctlnode node; 386 struct piixpcib_softc *sc; 387 uint8_t state, state2; 388 int ostate, nstate, error; 389 390 sc = speedstep_cookie; 391 error = 0; 392 393 state = piixpcib_get(sc); 394 if (state == PIIXPCIB_SPEEDSTEP_HIGH) 395 ostate = 1; 396 else 397 ostate = 0; 398 nstate = ostate; 399 400 node = *rnode; 401 node.sysctl_data = &nstate; 402 403 error = sysctl_lookup(SYSCTLFN_CALL(&node)); 404 if (error || newp == NULL) 405 goto out; 406 407 /* Only two states are available */ 408 if (nstate != 0 && nstate != 1) { 409 error = EINVAL; 410 goto out; 411 } 412 413 state2 = piixpcib_get(sc); 414 if (state2 == PIIXPCIB_SPEEDSTEP_HIGH) 415 ostate = 1; 416 else 417 ostate = 0; 418 419 if (ostate != nstate) 420 { 421 if (nstate == 0) 422 state2 = PIIXPCIB_SPEEDSTEP_LOW; 423 else 424 state2 = PIIXPCIB_SPEEDSTEP_HIGH; 425 426 error = piixpcib_set(sc, state2); 427 } 428 out: 429 return (error); 430 } 431
Indexes created Fri Sep 26 08:10:20 GMT 2025